Reconfiguration latency

Hey all,

I am playing with reconfiguring the USRP while its running and I was
trying to
figure out some kind of benchmark time (on the order of…?) that it
might take
to reconfigure different settings for the USRP.

(1) frequency
(2) interpolation / decimation
(3) mux
(4) etc.

I know that when you use the wfm GUI’s these parameters can be set
“instantly”
from a user point of view, but I’m a little more interested in a more
numerical
answer (more on the ms or us level…or clock cycle!) I realize the
latency is
much
longer the first time you set the USRP, but I’m more concerned with
REconfiguration.

In the case of the receive “set_freq” method for the RFX900, I have
looked
through some of the code, and it seems like there is a function in
db_flexrf.py
that writes to the FPGA registers _write_all that appears to be the
final step
before heading to the FPGA. Is this right?? I tried to put some print
statements ( print time.time() ) in the code to do an informal time test
to see
how fast it might take, but it didn’t work…so either I’m wrong about
this
method being involved in setting the frequency or I’m editing the wrong
document. (FYI, I used the script in the
…/site-packages/gnuradio/db_flexrf.py folder).

Going along with the idea of latency in the reconfiguration process, I
was
wondering if you loose samples while changing settings or is it pretty
seemless
(i.e. in
the case of decimation, I’m guessing there is a significant time lag to
reset
the FPGA decimators, but in the case of setting the carrier frequency, I
would
expect there to be less loss of data and more than likely less latency),
or
perhaps there is a buffer that holds the data until its ready to run
again?

Any help on quantifying the latency, and perhaps some help understanding
what
happens at the bit level to the samples in the FPGA during
reconfiguration would
be most appreciated.

THANKS,

David S.

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