It is unfortunate (at least for me) that the use of the Spartan-2000
precludes the use of the the web-pack tools from Xylinx. I’m sure that
the extra capacity will be welcome to those who can use it. I had been
planning to purchase a USRP2 system when they became available. But as
an individual unaffiliated with a university or a profit making
engineering firm, this appears to be unrealistic.
- Just use the prebuilt FPGA images we provide
To what end? Just to duplicate the efforts of others?
- Purchase the full version of ISE from Xilinx
Way out of the question. I spend entirely foolish amounts of money on
such things already, but this would break the bank. With no prospect of
return, even I can’t rationalize this.
- Get a 60 day demo version from the Xilinx Web S.
60 days to conceive, implement, and debug - it can take 60 days to get
tools of this scale installed correctly.
- Convince your Xilinx apps engineer to get you a free copy
Fat chance!
- Universities often get the tools free of charge
Not a viable option in my case.
- Release your changes to the community and we can find some sort of
way
to build them for you (if anybody wants to work on putting together
some
scripts to do this automatically, let me know).
An appealing idea, and it fits the community model well, but even if it
doesn’t get the wind up the skirts of the legal types at Xylinx to have
their tools used in this way, I find it difficult to imagine how this
would not be cumbersome to the point of unusability.
Still hoping for an alternative…
Dave Witten
On Sat, Sep 20, 2008 at 11:00 AM, David M. Witten II
[email protected] wrote:
It is unfortunate (at least for me) that the use of the Spartan-2000
precludes the use of the the web-pack tools from Xylinx. I’m sure that the
extra capacity will be welcome to those who can use it. I had been planning
to purchase a USRP2 system when they became available. But as an
individual unaffiliated with a university or a profit making engineering
firm, this appears to be unrealistic.
Will support for this FPGA appear in future versions of the free
tools? If so, does anyone have an idea of when this will happen.
Philip
I always find it difficult to reconcile what the manufacturer stamps ton
these products with marketing’s product briefs and what everyone calls
them (no matter which FPGA vendor), but this appears to refer to the
XC3S2000 product, part of the basic Spartan 3 series. This looks to be
just above the middle of the product line. If past experience is any
indication, when they well provide free support for these when the next
generation of products gets rolled out, maybe 6 - 18 mo.
– Dave
David,
I understand your frustration. Please understand that this decision was
not made lightly. We started out with the Spartan 3-1500 which is the
largest chip supported by the free tools. As we progressed, it became
apparent that there was not enough Block RAM to cram in all firmware for
the functionality we wanted at the same time.
I have some comments on your comments below, plus another possible
solution at the end…
David M. Witten II wrote:
- Just use the prebuilt FPGA images we provide
To what end? Just to duplicate the efforts of others?
You should note that the vast majority of users of the original USRP
never needed to use anything other than the standard FPGA build which we
provided, and we anticipate that will be the case with the USRP2.
Remember, the easiest place to do all of your processing is in the host
computer, and we provide standard images which will allow you to do
that. Even the guys who built that complete GSM basestation out of a
USRP1 used the standard FPGA build. Also note that you can still write
your own firmware for the processor in the FPGA, you just couldn’t
change logic around.
- Get a 60 day demo version from the Xilinx Web S.
60 days to conceive, implement, and debug - it can take 60 days to get
tools of this scale installed correctly.
I believe that you can get a new license repeatedly, so you could
“renew” every 60 days without reinstalling the tools. I realize that
this is not optimal.
Still hoping for an alternative…
Well here is one alternative. The S3-1500 is pin compatible with the
- If enough people wish to purchase a special version with the
smaller FPGA I can have a number of them built that way. You would have
to do some work to save a few block RAMs, but this isn’t impossible. My
last version that used the 1500 (rev 1) should still be in the
repository.
Please let me know what you think.
Matt
I see an emotional decision being considered and not necessarily a wise
business decision and one that involves more than Ettus, Inc. Open
Source
software, which I live and breathe for, does not mean free. It is
certainly
not free to you, Matt, when you have to support multiple versions of the
hardware. It is not free to the developers who support GnuRadio, day in
and
day out, spending their personal time, their employers time, etc. to
write
code for these devices.
On the Xilinx software, indeed, you can redo the demo versions
repeatedly.
My opinion is, it is what it is, you made the right design decision to
give
all of us sufficient capability to do all of those things that will
allow
those of us who are pursuing (with a dogged vengeance) the manufacture
of
one stop shopping for radio infrastructure, here in gnuradio.
I would oppose your well intentioned expenditure of time on this. You
just
got the USRP2 out the door, and within a short time, there is little
doubt
in my mind that the part will be supported by the free tools in a fairly
short time as other parts have in the past.
You cannot please everyone all of the time and this hardware and this
software project are doing “the good work” that needs doing for the vast
majority of the users/supporters here.
Bob
ARRL SDR Working Group Chair
Member: ARRL, AMSAT, AMSAT-DL, TAPR, Packrats,
NJQRP, QRP ARCI, QCWA, FRC.
“Trample the slow … Hurdle the dead”
On Sat, Sep 20, 2008 at 1:58 PM, Matt E. [email protected] wrote:
[snip]
Well here is one alternative. The S3-1500 is pin compatible with the 2000.
If enough people wish to purchase a special version with the smaller FPGA I
can have a number of them built that way. You would have to do some work to
save a few block RAMs, but this isn’t impossible. My last version that used
the 1500 (rev 1) should still be in the repository.
If it were the case that downgrading the FPGA made it reasonable ot
use a wholly free software toolset for building the FPGA images I’d be
behind doing that, and I’d put my own money behind supporting the
result.
But when degrading the USRP2 only means that you’d get more chose
among proprietary build tools, or the ability to skip constantly
reinstalling some nag-ware, it’s not that much of a win.
I’d rather see Matt’s time spent ensuring his own success, and perhaps
figuring out how to keep the total cost of a USRP-n system within the
reach of non-professional users. The FPGA build tools are not needed
by most users, and while it’s unfortunate that there choice of FPGA
results in additional difficulties for people interested in FPGA
modification, I do not think it is by far the biggest barrier to entry
for non-professional users.
Another suggestion is to contact your local Xilinx FAE and ask them for
a copy of the tool set for the larger FPGA. Also ask them why they
don’t include the larger device in the no cost Web Pack. I never
understood why all the devices weren’t included in the Web Pack. The
higher end parts have better margin and only lead to more sales for
Xilinx.
I understand them wanting to sell a support contract. But for Open
Source/Student projects or corporate project where you don’t need
factory support, give us the tools.
Anyway, if enough people ask NICELY, perhaps Xilinx will add more parts
to future releases of Web Pack.
“David” == David M Witten [email protected] writes:
…
>> - Get a 60 day demo version from the Xilinx Web S.
David> 60 days to conceive, implement, and debug - it can take 60
days
David> to get tools of this scale installed correctly.
Read the license carefully. Some ISE versions, like the full one-year
license or the evaluation version coming with some kits, have a “time
based
license”. During the “licensed” time you can create new designs, the
programms theirself are not time limited.
After the licensed time you may not create new designs, but maintain
legally
started designs.
http://www.xilinx.com/ise/license/license.htm
Whether this is valid for the ISE evaluation too, I couldn’t find out.
Perhaps
someone with a recent evaluation license can do.
Bye
Uwe Bonnes [email protected]
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------