On Fri, Feb 25, 2011 at 8:32 PM, Josh B. [email protected] wrote:
In contrast, when setting the clock rate on the usrp-e100, the driver
will dynamically reprogram the registers on the clock generator to
obtain the desired rate. See application notes:
http://www.ettus.com/uhd_docs/manual/html/usrp_e1xx.html#changing-the-master-clock-rate
I’ve been getting the following error during make since I
changed the clock rate. Did I brick the FPGA? I can’t seem to
find the special pass-through image anywhere.
USRP-E100 clock control: VCO calibration timeout
Vitals:
GNU C++ version 4.5.2 20101204 (prerelease); Boost_104100;
UHD_003.20110226000831.77641c6
Linux version 2.6.35 (balister@astro) (gcc version 4.5.2 20101026
(prerelease) (GCC) ) #1 PREEMPT Fri Nov 5 08:56:09 PDT 2010
usrp_e100_fpga_compat3_feb_25.bin
Thomas