Re: [USRP-users] UHD Announcement - February 25rd 2011

On Fri, Feb 25, 2011 at 8:32 PM, Josh B. [email protected] wrote:

In contrast, when setting the clock rate on the usrp-e100, the driver
will dynamically reprogram the registers on the clock generator to
obtain the desired rate. See application notes:

http://www.ettus.com/uhd_docs/manual/html/usrp_e1xx.html#changing-the-master-clock-rate

I’ve been getting the following error during make since I
changed the clock rate. Did I brick the FPGA? I can’t seem to
find the special pass-through image anywhere.

USRP-E100 clock control: VCO calibration timeout

Vitals:

GNU C++ version 4.5.2 20101204 (prerelease); Boost_104100;
UHD_003.20110226000831.77641c6

Linux version 2.6.35 ([email protected]) (gcc version 4.5.2 20101026
(prerelease) (GCC) ) #1 PREEMPT Fri Nov 5 08:56:09 PDT 2010

usrp_e100_fpga_compat3_feb_25.bin

Thomas

On 02/28/2011 10:02 AM, Thomas T. wrote:

hardware changes.
USRP-E100 clock control: VCO calibration timeout

If you can talk to it, then its still fine. Can you talk?

I think my wait for lock() is messed up since my 52Mhz is dead on and
its still printing that.

-josh

This forum is not affiliated to the Ruby language, Ruby on Rails framework, nor any Ruby applications discussed here.

| Privacy Policy | Terms of Service | Remote Ruby Jobs