My project aims at programming the fpga as a fft-ifft block, but i am a
complete novice to the usrp, so as a basic first step, all i am trying
to accomplish is that i program the fpga as a simple 4-bit counter and
take in the data. I already have a code written ccs which works upon
this data and gives me results which help me on my work further. But
till date, I was using a signal generator to feed data to the DSK, but
now, I want the fpga to do the same. Once programmed, it should feed the
DSK with data, so for starters, I want to program it as a simple
counter. Later, I want to model the fpga as a fft-ifft block, which does
the fft-ifft as required on being fed by the data from the DSK. This is
what I am aiming at.
So, after building the radio, i tried running the sample examples as
given and they ran perfectly. So,
Brian, do u now intend to tell me that I should I try Matt’s usrp_std
and program the fpga with that. Even if I do that, how do I assign the
pins for the fpga, I mean, the external IO pins. Or is there any
relevant documentation on this anywhere?
Thanks a lot for the support.
First of all, thanks a lot Eric for last piece of advice, it helped a lot.
But it still did not clarify me completely. I am a complete novice to the
USRP, having got it a few days back. Ok, continuing with my last topic, can
you please tell me how do I program the fpga specifically as a counter? I
mean, I just wanted to know the steps involved in the process, like
generating the .rbf files. I am currently working on Quartus II Web Edition
Can you give a hint as to what exactly you are trying to accomplish
with your USRP setup? Unless you are already skilled with Verilog and
FPGA’s, it would seem like you have a serious potential to break your
The majority of your questions are related to how to run Quartus II
and the Altera website does a pretty good job documenting how that is
Upon doing this, how can I read the data being generated by the fpga and
display it in the time domain. Also, how do I do the pin assignment for the
Clarification of these basic doubts would do a world of good to my project.
To look at the data being generated by the FPGA, all you must do is
look at the interface connecting the FPGA to the AD9862 to a logic
analyzer, import it into your favorite graphing software, and there is
your time domain representation of your interpolated data before it
goes through the AD9862. I wouldn’t recommend doing something along
In fact, if you want to just see what would happen - I recommend you
start out with a simulation. I believe you an download ModelSim from
the Altera website for free and simulate the entire FPGA. I believe
Matt wrote a testbench for the top level that you can figure out.
Thanks a lot.