Re: problem with start/end of burst inband FPGA code



We’d greatly appreciate any help, thanks!

I noticed that you’re asserting ‘skip’ in the WAIT state for a starting
packet, and in the HEADER state for later packets. Without more code, I
can’t tell if this makes any difference. You might try rewriting it to
have the same state transitions and assertion of ‘skip’ for all packets
of a burst.


something like this:

modify the second half of HEADER state like:

if (fifodata[`STARTOFBURST] == 1)
    // new burst; use clk to decide whether to skip
    trash <= 0;
payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
reader_state <= TIMESTAMP;
rdreq <= 1;

and then change the WAIT state as:

    if (tx_strobe == 1)
        tx_empty <= 1 ;

    if (trash == 1) //skip second and later packets flagged as trash
       reader_state <= IDLE;
       skip <= 1;
    else if ((timestamp < (adc_time + `JITTER)
                            && (timestamp > adc_time))
                            || timestamp == 32'hFFFFFFFF)
        reader_state <= WAITSTROBE;
    // Wait a little bit more
    else if (timestamp > adc_time + `JITTER)
        reader_state <= WAIT;
    // Outdated
    else if (timestamp < adc_time)
        //skip start of burst, flag later as trash
       trash <= 1;
       reader_state <= IDLE;
       skip <= 1;