Re: Help with Verilog

Message: 2
Date: Fri, 10 Nov 2006 08:03:11 -0800
From: Eric B. [email protected]
Subject: Re: [Discuss-gnuradio] Re: Help with Verilog
To: seph 004 [email protected]
Cc: [email protected]
Message-ID: [email protected]
Content-Type: text/plain; charset=us-ascii

On Fri, Nov 10, 2006 at 12:55:06AM -0800, seph 004 wrote:

// USB Side of FIFO
assign have_space = 1’b1; //quick fix for now. (wrptr <= 4000) not


Setting have_space to a constant 1 effectively turns off flow control
from the host through the FX2 to the FPGA.

Thus, the host will blast away, and you’ll be left with only what fit
in the single FIFO. About 2048 samples IIRC.


Thanks for the response. I’m ok with this setup seeing as I’m only
sending about 1000 samples at the most. Because I’m using a RAM to trap
the samples, they wouldn’t be moving to the transmit chain immediately,
so there wouldn’t be more chances to send anything.

I tried implementing a similar instruction to the one that was already

assign have_space = (wrptr <= 4000);

I’m using a 4k ram module, and the wrptr is supposed to advance
everytime a sample is successfully received and written into memory.
This instruction doesn’t work though, and it causes the host to stall as
if samples aren’t being transferred. I thought that perhaps because
wrptr is a register, it was being initialised to some value higher than
4000, thus causing have_space to evaluate to zero. So, I tried:

assign have_space = wrptr ? (wrptr <= (4095-256)) : 1’b1;

if wrptr is zero or unknown, the expression should be false and
have_space would then be one. If wrptr was any non-zero and known value,
then it should check if it is less than the ram size. This also doesn’t
work, as samples aren’t being transferred to the FPGA. So for now, I’m
stuck forcing have_space to 1 to get samples onto the FPGA.