From: “Oussama S.” [email protected]
Subject: Re: [Discuss-gnuradio] Help with Verilog
To: “seph 004” [email protected]
Cc: [email protected]
Message-ID:
[email protected]
Content-Type: text/plain; charset=“iso-8859-1”
Hi Lance,
On 11/7/06, seph 004 [email protected] wrote:
changing register for now). I am using a slightly modified version of the
test_usrp_standard_tx program to test my FPGA build. So far though, none of
the signals I’ve tried to send have been transmitted (I have a scope on the
daughterboard output). Below is the modified module:
Did you make sure that the output debug pins, that your logic analyzer
is
connected to, have been enabled?
module tx_buffer
input wire [3:0] channels, input clear_status,reg [3:0] load_next;
load_next <= #1 4’d0;
4’d2 : tx_i_1 <= #1 ramdata;
end
else if(WR & ~write_count[8])
tx_underrun <= 1’b0;
.wraddress ( wrptr ),
// Debugging Aids
help would be greatly appreciated.Regards
Lance
Hi
Thanks for taking a look. I have made sure to enable my outputs, and I
can see the effects of changes to the verilog. I am still having trouble
with the transmitting though. I know what the wave I’m transmitting is
supposed to look like on the scope (it’s the same as the normal
std_2rxhb_2tx.rbf and the test_usrp_standard_tx.) the only difference is
my FPGA build will hold the signal in tx_buffer, instead of streaming to
the tx_chain module immediately.
Regards
Lance