Re: Generic finite state machine / Viterbi algorithm impleme

Here is an update on this project:

  1. Optional initial/final state for Viterbi (put a negative number if
    you don’t want to set it)

  2. Automated the process of FSM generation for any ISI channel and
    modulation size, so now this part is done for you, instead of having to
    generate the FSM file (with, say matlab) and then read it in python.
    This piece of code is in the file

  3. Wrote two examples on ISI equalization using Viterbi:,

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