What is the expected delay if I do the I/Q processing
in the PC instead?
Do you have any simple example how to perform complex
I/Q processing for the path RX->FPGA->PC->TX.
On Tue, Apr 10, 2007 at 10:22:35AM -0700, Shaiful
I want to control I/Q signal going through USRP by
path of DEMOD->RX->FPGA->TX->MOD, quite similar to
what have been done by Jon Jacky in the following
The main different is that I’m going to use I/Q
from analogue DEMOD instead of doing the digital
I’ve been thinking about the easiest way on how to
achieve this aim. Do I need to program the FPGA
Verilog or can I just get away with higher level
How about the delay for the processing, is it
to get less than 1 us delay?
To achieve 1us delay, you’ll need to keep all the
signal processing on
the FPGA. We can’t get to the host in back in that
Cardiff School of Engineering, UK
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