I’ve been pondering a few ways to do the wait and ramp down (wait
like 16 clocks and then ramp down by right shifting on each clock)- but
do so, I need to know what the last value was so I can shift it. Will
tx_i_/tx_q_ remain persistent between clocks (my deduction was yes?)
so, my plan here was to have a reg that holds a 4-bit counter that
15 whenever tx empty goes high/true and then just keep right shifting
appropriate value (based on load_next) until zero (or just keep shifting
until data since 0 >> 1 = 0- would that save on logic?).
Then I had one question- is there ever a situation where we’re out of
for any number of channels, but there’s still one transmitting (e.g. can
tx_empty ever be asserted when we’re feeding just one of the 4
destinations?). I’m under the (mistaken?) impression that tx_empty
when we stop feeding the buffer altogether (underrun)- so without doing
digging- do we fill zero’s to the channels we’re not using when we’re
feeding one of them?
With those answered, I think I can probably try and get a version done
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