Hi, I need some help for ram_loader.v. I have a bug with start-up of
the usrp2 and I think that ram_loader module may be the problem. Some
process in that file aren’t clocked. Can somebody knowing verilog
language help me. I know some, bug i’m not a expert, can a state
machine run without clock?
I think ram_loader have a problem because the usrp2 doesn’t start with
my u2_rev3.bin but the fpga is well programed. So if the ram_loader
doesn’t work, the firmware can’t be load. Or the ram_loader works well
with the cpld but the cpld can’t read and load the firmware from the SD
I can write on the sd card , the usrp2 can load u2_rev3.bin but not the
firmware. So the problem is not the compiled binary file but can be the
verilog program, the cpld or the firmware.
If somebody have an idea.