On Tue, Apr 6, 2010 at 08:19, Yan N. [email protected] wrote:
I’m trying to understand how Digital Down Conversion Implemented in
gr-sounder project. The DDC needs to be implemented in FPGA, but there isn’t
any module in FPGA configuration implementing DDC. How does the receiver in
gr-sounder implement Digital Down Conversion?
The gr-sounder component does not implement a DDC. The host code
issues a tune command to set the center frequency of the analog
daughterboard, then the entire baseband bandwidth of the downconverted
signal is correlated with the reference PN code at successive lags to
get the channel impulse response.