Questions on DDC in gr-sounder project

Dear all,

I’m trying to understand how Digital Down Conversion Implemented in
gr-sounder project. The DDC needs to be implemented in FPGA, but there
isn’t any module in FPGA configuration implementing DDC. How does the
receiver in gr-sounder implement Digital Down Conversion?

Thanks a lot in advance

Regards,
YanÂ

On Tue, Apr 6, 2010 at 08:19, Yan N. [email protected] wrote:

I’m trying to understand how Digital Down Conversion Implemented in
gr-sounder project. The DDC needs to be implemented in FPGA, but there isn’t
any module in FPGA configuration implementing DDC. How does the receiver in
gr-sounder implement Digital Down Conversion?

The gr-sounder component does not implement a DDC. The host code
issues a tune command to set the center frequency of the analog
daughterboard, then the entire baseband bandwidth of the downconverted
signal is correlated with the reference PN code at successive lags to
get the channel impulse response.

Johnathan

Thank you so much Johnathan. Is that means the signal is converted
before ADC? I’m quite confused about how the FPGA configuration connect
with host code. The FPGA bitstream is loaded by usrp.source_c or
usrp.source_s. Where is the FPGA bitstream loaded into? How does the
usrp source class load the FPGA bitstream?Â

Thanks,
Yan

----- Original Message -----
From: Johnathan C. [email protected]
Date: Tuesday, April 6, 2010 11:32 pm
Subject: Re: [Discuss-gnuradio] Questions on DDC in gr-sounder project
To: Yan N. [email protected]
Cc: [email protected]

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