There were just a couple of things I wasn’t sure about:
If the RX chain is disabled inside the FPGA, but a receive application
is still running on the host pc, will samples still arrive on the host
pc (like 16 bit zeros)?
If wrreq for the FIFO in the RX buffer module is de-asserted, but an
application is still running expecting samples, will there still be
samples with zero value arriving on the host pc?
What is the behaviour of a GNU Radio program when the sample flow is
interrupted? Does the program merely idle waiting for samples until it
is finished running?
Lastly, is it feasible to re-adjust the USRP’s RX chain to work with
12-bit samples directly from the ADC instead of 16-bit adjusted
samples? I have very little experience in the level of dsp happening in
the rx_chain module, but how difficult would it be to modify this and
other rx modules to work with 12 bit samples directly from the ADC and
still retain their functionality?
I was musing about the possibility of a very simple form of inband
signalling for the receiver section by processing the 12 bit received
samples and then appending 4 bit messages to them to make 16 bit
samples to send across the usb to be seperated on the host pc.