I’m trying build my own fpga bitstream by modifying usrp_sounder
project. I’ve saveral questions on the module master_control.
what store in reg_0, reg_1, reg_2, and reg3?
what assign to io_0 through io_3?
Can I monitor the signal from io_tx pins in daughter board by
What the difference of the two group of io_tx pins?
Thank you so much in advance!