Question on receiver tuning issue

Thank you so much Johnathan. Is that means the signal is converted
before ADC? I’m quite confused about how the FPGA configuration connect
with host code. The FPGA bitstream is loaded by usrp.source_c or
usrp.source_s. Where is the FPGA bitstream loaded into? How does the
usrp source class load the FPGA bitstream?Â

Thanks,
Yan

----- Original Message -----
From: Johnathan C. [email protected]
Date: Tuesday, April 6, 2010 11:32 pm
Subject: Re: [Discuss-gnuradio] Questions on DDC in gr-sounder project
To: Yan N. [email protected]
Cc: [email protected]

This forum is not affiliated to the Ruby language, Ruby on Rails framework, nor any Ruby applications discussed here.

| Privacy Policy | Terms of Service | Remote Ruby Jobs