Hi all,
I have some problems when compile the fpga source.
I open uhd-git\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf with quartus II
then compile meet a lot of errors which is the path error like that:
Error (10054): Verilog HDL File I/O error at rx_buffer.v(25): can’t open
Verilog Design File “…/…/firmware/include/fpga_regs_common.v”
when I fix the path problem then compile success. but the generated rbf
file
is different from the one in rbf directory.
I use the newest git version.
Why no one have the answer or have the same question?
99.9% of the people on this list have no experience building the
firmware or making
modifications to it, they just use the as-supplied firmware.
The way the fpga code is setup, it’s intended to be built with “make”
rather than the vendors
IDE, so it doesn’t surprise me that you get topology-related errors.
But that’s as much as I know.
I’ve never built it myself.
Also, the way FPGA “routers” work, there’s a certain amount of
Monte-Carlo decision making
done in the way paths are laid out. So two different “runs” with
exactly the same codebase
can yield different (but functionally identical) FPGA binaries. The
same thing happens with
PCB routers–press the “route” button, it will be very often route the
same circuit/physical placement
with different lines.