Hi everyone…
I am getting confused about the use of the parameter of sampling rate in
I really need to understand the sampling rate of the uhd sink and
source
and the sampling rate of the blocks in the flow graph and how to choose
those sampling rates.

Thanks a lot for you help!!

On Wed, Apr 11, 2012 at 8:53 AM, Javier S. [email protected]
wrote:

Hi everyone…
I am getting confused about the use of the parameter of sampling rate in
I really need to understand the sampling rate of the uhd sink and source
and the sampling rate of the blocks in the flow graph and how to choose
those sampling rates.

Thanks a lot for you help!!

Sample rate is a fundamental parameter of digital signal processing. Try
an
introductory DSP textbook, or the following articles:

Without a basic understanding of sampling theory or DSP you will have

–n

Hi…
I mean… the sampling rate of the uhd sink and source what refers
to…?
I’ve since in some documents that if you are transmitting , you have to
take in account that the DAC for output works at 128 M/s and the sample
rate for the UHD sink block has to be determined somewhow from that.

In the same way the ADC for reception works at 64 M/s and the sampling
rate
for the UHD source block has to be determined somehow from that 64 M/s .

I just want to make simple transmission and reception.

Am I wrong? or I am understanding not really good what I am reading

On Wed, Apr 11, 2012 at 9:14 AM, Javier S. [email protected]
wrote:

I just want to make simple transmission and reception.

Am I wrong? or I am understanding not really good what I am reading about

Don’t worry about the USRP native rate (64/128Msps). The FPGA inside the
USRP handles interpolation and decimation to step from the sample rate
of
the USB interface (0.5Msps to 8Msps) to the ADC/DAC rate
(64Msps/128Msps).
The sample rate you choose should be the sample rate that is appropriate

–n

hi all ,

Don’t worry about the USRP native rate (64/128Msps). The FPGA
inside the USRP handles interpolation and decimation to step from the
sample rate of the USB interface (0.5Msps to 8Msps) to the ADC/DAC rate
(64Msps/128Msps). The sample rate you choose should be the sample rate
that is appropriate for your application.

i think this is correct provided that you consider that the
interpolation or decimation has a maximum value which is i think equal
to 400 ,
is this true Nick???
regards ,
Osama

Date: Wed, 11 Apr 2012 09:23:35 -0700
From: [email protected]
To: [email protected]
CC: [email protected]

On Wed, Apr 11, 2012 at 9:14 AM, Javier S. [email protected]
wrote:

Hi…
I mean… the sampling rate of the uhd sink and source what refers
to…? I’ve since in some documents that if you are transmitting , you
have to take in account that the DAC for output works at 128 M/s and
the sample rate for the UHD sink block has to be determined somewhow
from that.

In the same way the ADC for reception works at 64 M/s and the sampling
rate for the UHD source block has to be determined somehow from that 64
M/s .

I just want to make simple transmission and reception.

Am I wrong? or I am understanding not really good what I am reading
Don’t worry about the USRP native rate (64/128Msps). The FPGA inside the
USRP handles interpolation and decimation to step from the sample rate
of the USB interface (0.5Msps to 8Msps) to the ADC/DAC rate
(64Msps/128Msps). The sample rate you choose should be the sample rate
that is appropriate for your application.

–n

On Wed, Apr 11, 2012 at 10:58 AM, Nick F. [email protected] wrote:

On Wed, Apr 11, 2012 at 8:53 AM, Javier S. [email protected]
wrote:

Hi everyone…
I am getting confused about the use of the parameter of sampling rate in
I really need to understand the sampling rate of the uhd sink and
source and the sampling rate of the blocks in the flow graph and how to
choose those sampling rates.

Thanks a lot for you help!!

Sample rate is a fundamental parameter of digital signal processing. Try
an introductory DSP textbook, or the following articles:

http://en.wikipedia.org/wiki/Sampling_ratehttp://en.wikipedia.org/wiki/Nyquist–Shannon_sampling_theorem

http://en.wikipedia.org/wiki/Sampling_(signal_processing)http://en.wikipedia.org/wiki/Aliasing

Without a basic understanding of sampling theory or DSP you will have
–n

[email protected]

2012/4/12 osama mohamed [email protected]

or decimation has a maximum value which is i think equal to 400 ,
is this true Nick???
regards ,
Osama

Yes, there are practical limits to the decimation/interpolation rates
you
can choose. In general, you want to pick an even
decimation/interpolation,
and in general, you want to pick a rate that is divisible by 4. This
enables the use of both the halfband filters. Valid
decimation/interpolation values range from 4 to 512.

–n