I’m attempting to expand on a custom FPGA build I’ve been working on.
The function I’ve implemented is to write a set of data at run time to a
RAM created on the USRP FPGA. I used the usrp_tx chain functions
(modified buffer module) to achieve this.
I’ve successfully managed to load the RAM with 512 samples and 256
samples, but when I attempt to load in larger data sets (1024 and up), I
find that no more than 512 samples get transferred despite that fact
that all the address widths, counters and the memory size itself should
be more than sufficient to support the increased data volume.
I made a mod to attempt to check whether all the data was making it into
the FPGA by debug monitoring the txfifolevel parameter of the tx_buffer
module’s 4k FIFO. I find that value seems to fluctuate every time I run
the program though, which makes me wonder whether the FIFO isn’t being
cleared when I restart the program, even though I see the reset lines go
Has anyone attempted similar functionality? Are there any recommended
tests I could perform to diagnose the root of the problem?