I’m trying to put the Barker correlator in the FPGA. This should greatly
improve the SNR of the BBN 802.11 code.
The plan is:
64Msps complex w/11MHz info -> Barker Correlator -> Decim by 16 -> 4Msps
complex with 1MHz info
64Ms complex w/11MHz info -> Decim by 8 -> 8Msps complex with 11MHz info
-> Barker Correlator
I resampled the 11-bit Barker code to 64 taps (is this even the right
thing to do? MATLAB still gave me all real numbers) and used the Altera
IP FIR compiler to build a multiplier-less FIR. However, this FIR, when
I set everything to bit-width 16 (dropping all but the most significant
16 of the output), uses ~1/3 of the LEs of the FPGA. Is this expected or
did I do something grossly wrong?
In any case, I’m going to need at least 2 of them, one for TX and one
for RX, and quite possibly 4 if I have to stick one each on the input
and output I and Q paths. I definitely don’t have that much room, and
I’ve already removed the secondary RX and TX paths in the core.
If I let the FIR do some of the decimation, I can make it smaller, but I
don’t understand the DSP enough to know that that’s ok.
Also, I’m currently planning on inserting the FIR after the CORDIC and
before the CIC decimation filter. Is that the right place? If I put it
before the CORDIC then maybe I would only have to use 1 FIR on the RX