The FPGA on USRP1 sends an extra two bits of data with each 16-bit word
(to the FX2 chip). If I’m not mistaken, the first bit is set when
accompanying a sample from rx channel 0, and the second bit is set when
accompanying an inphase (as opposed to quadrature) sample (presumably
from channels 0, 2, 4, or 6).
- What significance do these two bits have in the handling of the data
after the FPGA?
I’m trying to figure out how best to set these bits in the case of
packed samples at lower quantization levels.