Programming USRP as a relay node

Hello everyone,

I am a postgraduate student at Technical University of Crete, Chania and
i am currently working on a project with USRPs. Part of our project is
to communicate with a relay node. But this relay node is a little bit
slow, because there is data transfer from USRP to PC and then from PC to
USRP. So, there is an idea to program the FPGA of USRP as a relay
without any communication between PC and USRP - the relay node just
detects packets and retransmit them without any further processing.

  1. One idea is to program the FPGA to include a packet detector and a
    raised cosine filter. But I read somewhere that the default FPGA has
    only 5% available resources and i am wondering if these resources are
    enough for a packet detector and a raised cosine filter?

  2. In case there are enough resources (in some way), could anyone
    estimate how difficult would be to implement it? Has the current
    configuration to be changed a lot or including the appropriate modules
    is enough?

I know that my questions are kind of abstract but i couldnt express them
differently

Thanks anyway

Tasos Kyrillidis


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On Sat, 2009-07-04 at 14:15 +0300, Tasos Kyrillidis wrote:

  1. One idea is to program the FPGA to include a packet detector and a
    raised cosine filter. But I read somewhere that the default FPGA has
    only 5% available resources and i am wondering if these resources are
    enough for a packet detector and a raised cosine filter?
    You can free up resources by reducing the number of channels.
    In your case, only one RX and one TX channel in stead of two.
    You can also replace the halfband filter with a raised cosine filter.
    (Note, you can only use a limited number of taps, depending on the
    decimation factor)

A simple signal level detector should be doable.
For a packet detector and best S/N ratio you should completely
demodulate the packets and remodulate them (regenerate the signal)
This will be quite complicated though and possibly not fit in the FPGA.

When you use a USRP2 you have much more room in the FPGA. Implementing a
complete receiver, packet detector and transmitter will certainly fit,
but it will still be a complicated design.

Greetings,
Martin

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