I am a postgraduate student at Technical University of Crete, Chania and
i am currently working on a project with USRPs. Part of our project is
to communicate with a relay node. But this relay node is a little bit
slow, because there is data transfer from USRP to PC and then from PC to
USRP. So, there is an idea to program the FPGA of USRP as a relay
without any communication between PC and USRP - the relay node just
detects packets and retransmit them without any further processing.
One idea is to program the FPGA to include a packet detector and a
raised cosine filter. But I read somewhere that the default FPGA has
only 5% available resources and i am wondering if these resources are
enough for a packet detector and a raised cosine filter?
In case there are enough resources (in some way), could anyone
estimate how difficult would be to implement it? Has the current
configuration to be changed a lot or including the appropriate modules
I know that my questions are kind of abstract but i couldnt express them
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