I am currently working on the USRP N210. I am trying to modify the VHDL
for the FPGA in order to gain acccess to some of the unused pins. I am
unsure of how to do this, and I was wondering if anyone had any advice
how to do this. I would greatly appreciate any help. Thank you.
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The Verilog code is all available and it is in the UHD git repository.
would suggest you start there.
Also here’s a link to a great paper containing a good analysis of how
all the HDL modules come together. Worth reading to get a head start
but you definitely will want to also look at the code in Xilinx ISE.
FYI you need the full version of ISE to program to the N210. FYI2 the
usrp-users mailing list is more appropriate for USRP hardware