Problems compiling testbench for USRP

Hello all,

I’ve been trying to use some of the test benches provided from Ettus’
site, in
the “fpga/tb” directory. I’m using Quartus II and ModelSim with the
latest
version of the fpga code.

I’m assuming that fullchip_tb.v is the test bench for the full
fpga. However,
the test bench seems to be written for a different module; The test
bench
doesn’t interface directly with usrp_std, and instead instantiates
“fullchip”.
The ports are similar to usrp_std, but not the same. Was the test bench
written
for something else?

Any additional info on the test benches (even a link) would be greatly
appreciated.

Nelson.

The USRP1 testbench code is not up to date with the design itself. You
would need to modify it to get it to work.

Matt

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