Problem of compiling FPGA bin files

GNU Radio
1

Hi,
I tried to use Xilinx ISE 11.1 to open project
“usrp2/fpga/top/u2_fpga/u2_fpga.ise”.There are some files missing,such
as"fifo_generator_4_1.v" . And there are errors when implement design…

==============================================
ERROR:ConstraintSystem:59 - Constraint <NET “adc_a[0]” LOC = “A14” ;>
[u2_fpga.ucf(1)]: NET “adc_a[0]” not found. Please verify that:

  1. The specified design element actually exists in the original
    design.
  2. The specified object is spelled correctly in the constraint source
    file.
    …
    ERROR:ConstraintSystem:59 - Constraint <NET “clk_muxed” TNM_NET =
    “clk_muxed”;>
    [u2_fpga.ucf(216)]: NET “clk_muxed” not found. Please verify that:
  3. The specified design element actually exists in the original
    design.
  4. The specified object is spelled correctly in the constraint source
    file.
    …
    ERROR:ConstraintSystem:59 - Constraint <NET “ser_t<15>” IOSTANDARD =
    LVCMOS25
    |> [u2_fpga.ucf(336)]: NET “ser_t<15>” not found. Please verify
    that:
  5. The specified design element actually exists in the original
    design.
  6. The specified object is spelled correctly in the constraint source
    file.
    …
    ERROR:ConstraintSystem:59 - Constraint <DRIVE = 12 |>
    [u2_fpga.ucf(336)]: NET “ser_t<15>” not found. Please verify that:
  7. The specified design element actually exists in the original
    design.
  8. The specified object is spelled correctly in the constraint source
    file.
    …
    ERROR:ConstraintSystem:59 - Constraint <SLEW = FAST ;>
    [u2_fpga.ucf(336)]: NET “ser_t<15>” not found. Please verify that:
  9. The specified design element actually exists in the original
    design.
  10. The specified object is spelled correctly in the constraint source
    file.
    =========================================

How could I fix it??

Thanks!

Liang

2

Some people have had success with ISE 11.1, and some have not. I have
not tried it yet, and am still on 10.1.03 which is known to work. Early
in the new year I’ll be moving to 11.1, but if anyone can figure out the
problems, that would be much appreciated.

Matt

3

Who has had success with 11.x? I’m eager to start working with the
usrp2 code, but I cannot get the tools to work.

I was on the phone today for 30 minutes with the local Xilinx sales
rep and they just won’t allow me to get 10.1.03. You can’t buy it, you
can’t get it for free, and you can’t even get it unofficially. They
only offer the 11.x series ISE.

juha

2009/12/3 Matt E. [email protected]:

4

Juha-

Who has had success with 11.x? I’m eager to start working with the
usrp2 code, but I cannot get the tools to work.

I was on the phone today for 30 minutes with the local Xilinx sales
rep and they just won’t allow me to get 10.1.03. You can’t buy it, you
can’t get it for free, and you can’t even get it unofficially. They
only offer the 11.x series ISE.

Suggest the following:

  1. Tell your Xilinx sales rep to either a) help you with issues in
    porting from 10.1.03 to 11.1, or b) give you 10.1.
    His argument is based on expected user ability to port. If he really
    thinks it’s easy, then it’s easy for him to help
    you.

  2. Post your specific porting issues on comp.arch.fpga. Xilinx has a
    couple of guys there who are helpful, plus you
    are likely to get peer suggestions.

Since 1998, my experience has been that each new version of ISE is
always a porting headache. This has historically
been a fundamental Xilinx issue.

-Jeff