Phase ambiguity w/o RF daughterboards?

I set up a USRP1 with 2 BasicRX daughterboards configured, each
configured
in dual-channel complex mode (mux is 0x3210). My application is modified
from usrp_oscope.py to actually work in this mode. For instance, the
set_freq and set_gain functions actually apply to all the subdevs not
just
the first one. I set the subdev list to (0,0) (0,1) (1,0) and (1,1).

The application simply takes the two complex streams and subtracts them,
and then plots the magnitude of the output on the scope.

To test the app, I set up a dual-channel 16 MHz signal generator with
0.05 V sine waves out each input, and connected it to inputs 0 and 2.

When I tune the USRP to different frequencies (e.g., 16M, 16.1M, 15.9M,
16.5M, etc), I get very different amplitudes and the FFT coefficients
change dramatically. I see swings of 3-10 dB. The amplitude is not
constant for a given frequency, but seems to depend on what frequency
was previously used.

When I look at either individual stream, but not their difference, the
amplitude stays constant accross frequency.

My first thought was that this sounded like the problems with MIMO, that
retuning the frequency would introduce unknown (but constant) phase
offset
between the streams and they might sometimes be constructive and other
times destructive. But the mailing list archive seems to treat this
phase
offset as coming from the RF oscillators and their PLL to the master
clock, rather than from the AD9862 or other features. BasicRX has no
such
oscillator.

Are there other ways for phase ambiguity to crop up differently for the
2
daughterboards even when using Basic RX boards? Any suggestions for
what
else I should test?

Thanks,
Dan

On 08/26/2010 04:48 PM, Daniel H. wrote:

To test the app, I set up a dual-channel 16 MHz signal generator with

2 daughterboards even when using Basic RX boards? Any suggestions for
what else I should test?

Thanks,
Dan

The USRP1 is set up to use 2 separate DDCs with separate phase
accumulators. Every time you set them, there is a varying amount of
time between setting one and setting the other, which gives rise to the
phase difference. Typically in a MIMO system you don’t care about the
absolute phase difference as long as it stays constant, which it will if
you don’t retune.

If you need a constant phase difference then you can modify the FPGA
code so that the 2 DDCs share the same phase accumulator. This is a
very trivial change.

Matt

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