On 3/4/07, [email protected] [email protected] wrote:
It’s a very nice chip, but it appears to be very expensive at $38… =(
TI’s costs $7, which is quite affordable.
You get a lot for not a lot of money in comparison to writing and
validating your own Transaction and Data Link layers for a PCIe PHY.
If simplicity is your friend, the extra $31 might possibly be the best
money you could spend.
On the other hand, if you don’t even want to pay $7 for a PCIe PHY -
Lattice Semiconductor makes a low cost FPGA with DSP blocks (MAC
included, not just MULT) that also have SERDES lines to them.
You can even get a quick PCIe dev board from them here:
I’m not sure how to address the IP core issue yet. The Open Graphics
project will have to deal with it sooner or later, but I hope we will
coordinate efforts. I told them what I had discovered so far, but I’ll
have to see how that discussion turns out before I can say if it’ll be
any help. If you know anything about the problems I need to solve, I’d
love to hear about it.
I am not sure how their IP solution works, but you can try to contact
their representatives and try to help figure it all out. It might be
I don’t have a site yet since so far I have little but a fuzzy picture
of what I want to do. I’m still trying to find out if it is actually
even doable. The hardware seems possible, even for $100 if I use a
slightly cheaper ADC than I’d like, but to then process this massive
amount of data I’m rather unsure about. I emailed the FFTW project,
since I figure they’re the experts, but as of yet I’ve seen no reply.
Might be there’s no one checking emails at weekends…
Anything with embedded mults and a clock rate 10 to 20 times higher
than your maximum bandwidth would probably be really good - at least
for fixed point processing (which I highly recommend).
Once I have gathered a little more real data and can come up with a
workable plan I’ll probably set up a site of some sort. Maybe a simple
Sounds cool - keep me informed, please!
Thanks for the reply!