PCIe know-how?


#1

Hello,

I’m trying to create a low-cost (below $100€) Software Defined
Radio/Spectrum Analyser/Oscilloscope using a high-speed AD converter,
an FPGA, and the PCIe bus. It would be Open Hardware and compatible
with the efforts of the GNU Radio group.

I don’t have a lot of experience with this sort of thing, but by using
existing Open Source solutions I think it should be possible. Since
your project deals with both FPGAs and the PCIe bus I was wondering
what existing efforts of yours’, or existing know-how, I could use for
my own project? Do you have any solutions in mind I could re-purpose
or benefit from?

Sincerely,

Nos


#2

On 3/4/07, removed_email_address@domain.invalid removed_email_address@domain.invalid wrote:

what existing efforts of yours’, or existing know-how, I could use for
my own project? Do you have any solutions in mind I could re-purpose
or benefit from?

Sincerely,

Nos

Hm. Looks like I got my mailing lists crossed. This was intended for
the Open Graphics list, but at least you know what I’m trying to do
now… Anyone interested?


#3

On Sun, Mar 04, 2007 at 08:44:59PM +0200, removed_email_address@domain.invalid wrote:

your project deals with both FPGAs and the PCIe bus I was wondering
the Open Graphics list, but at least you know what I’m trying to do
now… Anyone interested?

Sure, I’m interested.

We’ve got tons of signal processing code that could be useful, and of
course you are free to reuse it all under the terms of the GPL.

Keep us posted regarding your project, and feel free to discuss
both the h/w and s/w here. The more the merrier.

Eric


#4

With regards to the PCIe interface, were you looking more at just
getting a PHY transceiver and putting the MAC and other layers in the
FPGA, or were you more interested in having a PCIe bridge chip that
handles all of that for you?

I know Philips and TI have PCIe transceivers which work with Xilinx
and Altera IP for the MAC layer, but what I really found interesting
was a PCIe bridge chip from PLX technologies. It’s a relatively hefty
BGA, but if you can place it properly the chip could really be a huge
help. No NDA’s are required and the information can be found here.

http://www.plxtech.com/products/expresslane/pex8311.asp

Do you have a place where you are hosting your thoughts/ideas on the
subject, or just some e-mail threads?

Brian


#5

On 3/4/07, Brian P. removed_email_address@domain.invalid wrote:

http://www.plxtech.com/products/expresslane/pex8311.asp

Do you have a place where you are hosting your thoughts/ideas on the
subject, or just some e-mail threads?

Brian

It’s a very nice chip, but it appears to be very expensive at $38… =(
TI’s costs $7, which is quite affordable.

I’m not sure how to address the IP core issue yet. The Open Graphics
project will have to deal with it sooner or later, but I hope we will
coordinate efforts. I told them what I had discovered so far, but I’ll
have to see how that discussion turns out before I can say if it’ll be
any help. If you know anything about the problems I need to solve, I’d
love to hear about it. :slight_smile:

I don’t have a site yet since so far I have little but a fuzzy picture
of what I want to do. I’m still trying to find out if it is actually
even doable. The hardware seems possible, even for $100 if I use a
slightly cheaper ADC than I’d like, but to then process this massive
amount of data I’m rather unsure about. I emailed the FFTW project,
since I figure they’re the experts, but as of yet I’ve seen no reply.
Might be there’s no one checking emails at weekends…

Once I have gathered a little more real data and can come up with a
workable plan I’ll probably set up a site of some sort. Maybe a simple
blog.

Thanks for the reply!


Nos


#6

On Sun, Mar 04, 2007 at 04:14:33PM -0500, Brian P. wrote:

http://www.plxtech.com/products/expresslane/pex8311.asp

Interesting part. Thanks for the pointer.

The Xilinx Virtex-5 LXT’s and SXT’s have (or will have) hard PCIe
endpoint blocks. This puts most of endpoint IP into dedicated silicon.

              slices    DSP48 blocks  10/100/1000    Rocket IO
                        550 MHz       ethernet MACs

XC5VSX35T 5,400 192 4 8
XC5VSX50T 8,160 288 4 12
XC5VSX95T 14,720 640 4 16

I’m sure they’re not cheap, but that’s a lot of DSP resources :wink:

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/Virtex-5_LX_LXT_SXT_Product_Table.pdf

Eric


#7

On Mon, Mar 05, 2007 at 12:01:18AM +0200, removed_email_address@domain.invalid wrote:

help. No NDA’s are required and the information can be found here.

I’m not sure how to address the IP core issue yet.

That’s what the $38 is buying you :wink:

The Open Graphics project will have to deal with it sooner or later,
but I hope we will coordinate efforts. I told them what I had
discovered so far, but I’ll have to see how that discussion turns
out before I can say if it’ll be any help. If you know anything
about the problems I need to solve, I’d love to hear about it. :slight_smile:

Eric


#8

On 3/4/07, removed_email_address@domain.invalid removed_email_address@domain.invalid wrote:

It’s a very nice chip, but it appears to be very expensive at $38… =(
TI’s costs $7, which is quite affordable.

You get a lot for not a lot of money in comparison to writing and
validating your own Transaction and Data Link layers for a PCIe PHY.
If simplicity is your friend, the extra $31 might possibly be the best
money you could spend.

On the other hand, if you don’t even want to pay $7 for a PCIe PHY -
Lattice Semiconductor makes a low cost FPGA with DSP blocks (MAC
included, not just MULT) that also have SERDES lines to them.

You can even get a quick PCIe dev board from them here:

http://www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2mpciexpressevaluation.cfm

I’m not sure how to address the IP core issue yet. The Open Graphics
project will have to deal with it sooner or later, but I hope we will
coordinate efforts. I told them what I had discovered so far, but I’ll
have to see how that discussion turns out before I can say if it’ll be
any help. If you know anything about the problems I need to solve, I’d
love to hear about it. :slight_smile:

I am not sure how their IP solution works, but you can try to contact
their representatives and try to help figure it all out. It might be
very interesting.

I don’t have a site yet since so far I have little but a fuzzy picture
of what I want to do. I’m still trying to find out if it is actually
even doable. The hardware seems possible, even for $100 if I use a
slightly cheaper ADC than I’d like, but to then process this massive
amount of data I’m rather unsure about. I emailed the FFTW project,
since I figure they’re the experts, but as of yet I’ve seen no reply.
Might be there’s no one checking emails at weekends…

Anything with embedded mults and a clock rate 10 to 20 times higher
than your maximum bandwidth would probably be really good - at least
for fixed point processing (which I highly recommend).

Once I have gathered a little more real data and can come up with a
workable plan I’ll probably set up a site of some sort. Maybe a simple
blog.

Sounds cool - keep me informed, please!

Thanks for the reply!


Nos

Brian


#9

On 3/4/07, Eric B. removed_email_address@domain.invalid wrote:

I’m sure they’re not cheap, but that’s a lot of DSP resources :wink:

You’ve got that right - they’re well into a couple hundred dollars
each. Wishful thinking, and I do salivate over those big FPGA’s - but
for a home project they seem pretty impractical (unfortunately) :frowning:

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/Virtex-5_LX_LXT_SXT_Product_Table.pdf

Eric

Brian


#10

On 3/4/07, Daniel O’Connor removed_email_address@domain.invalid wrote:

You would still need a PCI core although you can get those a lot cheaper than
PCIe cores. You can even get a free one from OpenCores (there is a PCI to
wishbone bridge for example).

I don’t think you need anything PCI with the specified PLX chip.

The PEX8311 has a description of:

"8/16/32-bit, 66MHz, Local Bus to PCI Express Bridge"

As far as I am aware there are no PCIe equivalents to the PLX 9054 (for
example) - ie PCIe to local bus bridges.

I believe that is an equivalent, but still relatively expensive in
comparison to just a PHY chip.

You might need some information about laying out your board for PCIe
compliance however you can probably glean that information from a PLX example
design :slight_smile:

Very true - they seem to have the board layout all right there from
their reference design development board. Pretty nice!


Daniel O’Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
“The nice thing about standards is that there
are so many of them to choose from.”
– Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

Brian


#11

On Monday 05 March 2007 11:26, Brian P. wrote:

I don’t think you need anything PCI with the specified PLX chip.

The PEX8311 has a description of:

"8/16/32-bit, 66MHz, Local Bus to PCI Express Bridge"

Whoops you are right.
Weird I haven’t seen that before on their site, maybe I’m going blind :slight_smile:

As far as I am aware there are no PCIe equivalents to the PLX 9054 (for
example) - ie PCIe to local bus bridges.

I believe that is an equivalent, but still relatively expensive in
comparison to just a PHY chip.

Yeah, but your average hobbyist can’t afford $100k for a PCIe core :wink:

You might need some information about laying out your board for PCIe
compliance however you can probably glean that information from a PLX
example design :slight_smile:

Very true - they seem to have the board layout all right there from
their reference design development board. Pretty nice!

Handy indeed :slight_smile:


#12

On Monday 05 March 2007 07:44, Brian P. wrote:

With regards to the PCIe interface, were you looking more at just
getting a PHY transceiver and putting the MAC and other layers in the
FPGA, or were you more interested in having a PCIe bridge chip that
handles all of that for you?

I know Philips and TI have PCIe transceivers which work with Xilinx
and Altera IP for the MAC layer, but what I really found interesting
was a PCIe bridge chip from PLX technologies. It’s a relatively hefty
BGA, but if you can place it properly the chip could really be a huge
help. No NDA’s are required and the information can be found here.

You would still need a PCI core although you can get those a lot cheaper
than
PCIe cores. You can even get a free one from OpenCores (there is a PCI
to
wishbone bridge for example).

As far as I am aware there are no PCIe equivalents to the PLX 9054 (for
example) - ie PCIe to local bus bridges.

You might need some information about laying out your board for PCIe
compliance however you can probably glean that information from a PLX
example
design :slight_smile:


#13

On 3/5/07, removed_email_address@domain.invalid removed_email_address@domain.invalid wrote:

I’ve been thinking about this since yesterday. With a lower resolution
like Brian suggested the data would fit over a Gigabit Ethernet link.
Further, GE carries 100 meters which would allow one to put the device
right at the antenna if one has a weatherproof enclosure. Supplying
power would be an issue still, but that’s easily overcome.
With some simple compression one might be able to accommodate a higher
performance ADC aswell, but that’s an issue I shouldn’t need to bother
with using 12 bits and 65MHz…

Power over Ethernet (PoE) can supply almost 13W of power (maximum). I
am not sure if that is really an option or being considered for the
next USRP, but it is a potential solution for delivering power to
remote devices.

http://en.wikipedia.org/wiki/Power_over_Ethernet

It’s a solution superior to PCIe in every way.

PCIe still has an advantage of much higher speeds and much lower
latency. On the flip side, you can’t put it 100m away.

Is there any work on this done already? If not, how do I start? =)


Nos

(I keep forgetting to add the cc. Sorry if I’m causing discontinuity.)

Brian


#14

On 3/4/07, removed_email_address@domain.invalid removed_email_address@domain.invalid wrote:

Oh yes! Sorry, forgot to mention that part.
I’d like to have an ADC with 65 to 105 Msps at 16 bits. This should
allow me to sample up to 30 or 50MHz respectively. I was inspired to
this from the Mercury project of the HPSDR, but that project relies on
a whole lot of other hardware, running at a total cost of some $500,
and it still relies on USB for the interface.

Just wondering - any reason why you want 16-bits of resolution? That
gives you ~96dB of dynamic range which is great, but do you really
need it? 12-bits should actually give you a really good amount of
dynamic range while keeping everything within budget. Even a 10-bit
solution would probably give you enough to be really good while
keeping everything on the cheap. I believe even those really
expensive Agilent or Tektronix oscilloscopes just use 8-bit
converters.

Maxim has a pretty decent selection of high speed ADCs. Which ones
did you have in mind that you were looking at?

now. Added value for later, I think. Right now I’m only interested in
shortwave transmissions, but the bandwidth of the ADC could surely be
used for other things aswell.

Those ADCs probably have a really wide analog bandwidth and allow for
“high IF” sampling - where the desired signal is located somewhere
higher than your sample rate, but the bandwidth of the signal is much
lower than your actual sampling rate. You then sample at a lower rate
than the IF and get an “image” of that actual signal - exploiting the
aliasing instead of trying to filter it out.


Nos

Brian


#15

just to stick my oar in…

Quoting Brian P. removed_email_address@domain.invalid on Sun 04 Mar 2007 22:47:36
GMT:

need it? 12-bits should actually give you a really good amount of
dynamic range while keeping everything within budget. Even a 10-bit
solution would probably give you enough to be really good while
keeping everything on the cheap. I believe even those really
expensive Agilent or Tektronix oscilloscopes just use 8-bit
converters.

this is a good idea, you will probably find that the analogue receive
chain
introduces so to much noise to make anything over 6 or 7 bits resolution
(at
best) meaningful anyway

lower than your actual sampling rate. You then sample at a lower rate
than the IF and get an “image” of that actual signal - exploiting the
aliasing instead of trying to filter it out.

you said earlier that this is a home project, do you mean you have no
intention
of (low volume) production? for a single board $100 is a very ambitious
target.
BGA packages usually need multilayer to escape the signals, and PCIe
needs
controlled impedance. you might find that the PCB tooling costs alone
exceed
your budget


Nos

Brian

if you can reduce your data rate so that gigE will do, it’s probably
worth
having a look for FPGA gigE development boards with an versatile i/o
header,
then designing a single layer (cheap) daughter board for the ADC.
otherwise
you’re probably best to wait for the gigE usrp.

(you might have to offer to do someones washing/cooking/cleaning to get
them to
sell it to you for $100 :slight_smile:

Jon


#16

The ADCs I’ve been looking at can apparently somehow sample
frequencies above their sampling rate aswell. I’m not really sure how
this works, but I don’t think it’s an issue I must bother with right
now. Added value for later, I think. Right now I’m only interested in
shortwave transmissions, but the bandwidth of the ADC could surely be
used for other things aswell.

You can use the wider analog bandwidth of the converter to undersample
your signal, assuming you use proper filtering.

Ryan


#17

On 3/5/07, removed_email_address@domain.invalid removed_email_address@domain.invalid wrote:

On 3/4/07, Eric B. removed_email_address@domain.invalid wrote:

There will be an version of the USRP available later this year that
has a gigabit ethernet interface. I’m hoping to be able to get
100MB/s through that.

Eric

I’ve been thinking about this since yesterday. With a lower resolution
like Brian suggested the data would fit over a Gigabit Ethernet link.
Further, GE carries 100 meters which would allow one to put the device
right at the antenna if one has a weatherproof enclosure. Supplying
power would be an issue still, but that’s easily overcome.
With some simple compression one might be able to accommodate a higher
performance ADC aswell, but that’s an issue I shouldn’t need to bother
with using 12 bits and 65MHz…

It’s a solution superior to PCIe in every way.

Is there any work on this done already? If not, how do I start? =)


Nos

(I keep forgetting to add the cc. Sorry if I’m causing discontinuity.)


#18

On 3/4/07, Eric B. removed_email_address@domain.invalid wrote:

course you are free to reuse it all under the terms of the GPL.
could refrain from the squeezing I’d save a whole lot of cash in
started. Lucky for me I love learning things that are of use! =)

There will be an version of the USRP available later this year that
has a gigabit ethernet interface. I’m hoping to be able to get
100MB/s through that.

Eric

Oh yes! Sorry, forgot to mention that part.
I’d like to have an ADC with 65 to 105 Msps at 16 bits. This should
allow me to sample up to 30 or 50MHz respectively. I was inspired to
this from the Mercury project of the HPSDR, but that project relies on
a whole lot of other hardware, running at a total cost of some $500,
and it still relies on USB for the interface.

0 to 30MHz would allow me to sample the entire shortwave band and
below simultaneously, so I could for example have code in place to
automatically decode and display every data transmission taking place,
if my CPU is up for it. Tuning would be instant; I could automagically
jump to new transmissions in the amateur bands, or click and drag on a
waterfall display to tune. If I can code that…

The ADCs I’ve been looking at can apparently somehow sample
frequencies above their sampling rate aswell. I’m not really sure how
this works, but I don’t think it’s an issue I must bother with right
now. Added value for later, I think. Right now I’m only interested in
shortwave transmissions, but the bandwidth of the ADC could surely be
used for other things aswell.


Nos


#19

On 3/6/07, Henry V. removed_email_address@domain.invalid wrote:

Hi,

You may have a look at and/or contact:

http://wwwhome.cs.utwente.nl/~ptdeboer/ham/sdr/

He is also using some basic Ethernet interface/-frame?

Henry.

I just sent him an email. He mentioned considering releasing the code
under the GPL, so I asked him if he’d do that, and/or let me base my
design on his.

I changed the URL of the blog to http://gnurillasdr.blogspot.com/
It’s a play on GNU, Guerilla Radio, and SDR. Now if I could still fit
a reference to Ether in there I’d be happy.

There’s some new and interesting info in the blog too. Aside from the
fine contributions from this list, I’ve found some very enlightening
videos discussing almost this exact issue we’re dealing with. =)

Thank you very much for the link!

Sincerely,

Nos


#20

Hi,

You may have a look at and/or contact:

http://wwwhome.cs.utwente.nl/~ptdeboer/ham/sdr/

He is also using some basic Ethernet interface/-frame?

Henry.