As per the advice given, I have started to try change the FPGA code to
bypass the DDC for the USRP2.
I am first trying to edit using the 30day trial for ISE v12 in Windows.
I have 2 questions,
I fail to locate the project file from the git.
I was wondering if the AeMB processor directly feeds off the output
the DDC module (i_out and q_out) or it only manages the flow of data?
thanks in advance
Cheaw Wen Guey