On Wed, Jul 9, 2008 at 11:40 AM, Chris S.
[email protected]lid wrote:
I am troubleshooting a problem with my GPS receiver. Is it possible to
collect some 64 MHz data? I understand the collect will not be long because
USB2 can’t handle the bandwidth, but perhaps buffers on the USRP will allow
me to make a 1ms collect?
You would have to modify the FPGA code to do so, but it is indeed
possible if not trivial.
The gr-radar-mono code does this (there are of course a lot of
unrelated customizations to the FPGA code as well). During the
interval in time the USRP is listening for radar echos, is streams
data at 64 Msps into a new FIFO, which accepts 1 sample per clock.
This FIFO is connected to the existing rx_buffer FIFO, which then
streams out the USB at 1 sample per 8 clocks. This implies it can
only sample at a maximum of 12.5% duty cycle. (The radar code uses
the gap to send its transmit pulse out and wait for the range gate to
Probably not what you wanted to hear
Corgan Enterprises LLC