No decimation -- collect at 64MHz

Hi,

I am troubleshooting a problem with my GPS receiver. Is it possible to
collect some 64 MHz data? I understand the collect will not be long
because USB2 can’t handle the bandwidth, but perhaps buffers on the USRP
will allow me to make a 1ms collect?

Thanks,

Chris

On Wed, Jul 9, 2008 at 11:40 AM, Chris S.
[email protected]lid wrote:

I am troubleshooting a problem with my GPS receiver. Is it possible to
collect some 64 MHz data? I understand the collect will not be long because
USB2 can’t handle the bandwidth, but perhaps buffers on the USRP will allow
me to make a 1ms collect?

You would have to modify the FPGA code to do so, but it is indeed
possible if not trivial.

The gr-radar-mono code does this (there are of course a lot of
unrelated customizations to the FPGA code as well). During the
interval in time the USRP is listening for radar echos, is streams
data at 64 Msps into a new FIFO, which accepts 1 sample per clock.
This FIFO is connected to the existing rx_buffer FIFO, which then
streams out the USB at 1 sample per 8 clocks. This implies it can
only sample at a maximum of 12.5% duty cycle. (The radar code uses
the gap to send its transmit pulse out and wait for the range gate to
arrive.)

Probably not what you wanted to hear :slight_smile:


Johnathan C.
Corgan Enterprises LLC
http://corganenterprises.com/

On Wed, Jul 9, 2008 at 11:18 PM, Chris S.
[email protected] wrote:

The gr-radar-mono code does this (there are of course a lot of
unrelated customizations to the FPGA code as well).

I’m going to look at this. I’ll be back with questions…

There are some nuances. The existing rx_buffer FIFO can only accept
samples at a maximum of 1 sample per 3 clocks. (In the standard build,
it never needs to go even this fast.) Rather than rewriting the
rx_buffer FIFO, which has a lot of Cypress FX2 battle scars in it, I
created a new FIFO (fifo32_2k.v), then joined it to the existing one.
So the 64 Msps samples go into the new FIFO, and a process streams
these out at 1/3 the clock rate into the existing FIFO. Finally, the
samples are streamed out to the USB controller at 1/8 the clock rate.
Look in radar_rx.v for this.

There is a state machine in radar_control.v that drives the
rx_control_o wire to enable all this.


Johnathan C.
Corgan Enterprises LLC
http://corganenterprises.com/

Thanks for your reply.

Johnathan C. wrote:

You would have to modify the FPGA code to do so, but it is indeed
possible if not trivial.

Trivial is good! However, for it would probably take two weeks to get
to the point where I can make the trivial change!

The gr-radar-mono code does this (there are of course a lot of
unrelated customizations to the FPGA code as well).

I’m going to look at this. I’ll be back with questions…

Chris

This forum is not affiliated to the Ruby language, Ruby on Rails framework, nor any Ruby applications discussed here.

| Privacy Policy | Terms of Service | Remote Ruby Jobs