I’ve just built and checked in new FPGA binaries based on Matt’s
changes over the past week or so.
The changes include fixes for the scaling in the CIC decimator so that
signals are now roughly leveled, independent of the decimation
rate. Decimating by 44 now works too
If you’re tracking svn, you’ll get these on your next update.
As always, if you run into any problems, please let us know.