On Tue, Jul 21, 2009 at 11:48, Jason U.[email protected] wrote:
Don’t all of the multi-antenna files require a specific FPGA build
(ie, unique to the USRP1) to get two real signals from a single
daughterboard? Is there such an FPGA build for the USRP2? (I ask
because the multi-antenna scripts don’t seem to represent that)
The current USRP2 FPGA build treats the Basic/LFRX as I and Q baseband
cards, with a single DDC for frequency conversion and sample rate
conversion, resulting in a single IQ stream over the GbE.
It is possible to write an FPGA image with 2 DDCs that have TX_A and
TX_B connectors routed individually as I channels (with Q set to 0.)
However, the current host interface does not provide a way to
independently set two different DDC parameters (frequency and
decimation) or to receive two sample streams.
Long term, this will get fixed when we have the VRT interface in release
Short term, there will be an alternate FPGA build that does the above,
but the two DDCs will share conversion frequency and decimation, and
will result in an interleaved I1Q1I2Q2 type stream. This would at
least allow coherently sampling two baseband inputs.