In the …\gnuradio-3.0.2\usrp\fpga\sdr_lib/master_control.v module, I
see settting_reg module is called as follow
setting_reg #(`FR_MASTER_CTRL)
sr_mstr_ctrl(.clock(master_clk),.reset(1’b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
However, in …\gnuradio-3.0.2\usrp\fpga\sdr_lib/setting_reg.v module,
the setting_reg module has “changed” output signal. Can anyone please
tell me what will happen to that “changed” signal?
The following is the setting_reg module
module setting_reg
( input clock, input reset, input strobe, input wire [6:0] addr,
input wire [31:0] in, output reg [31:0] out, output reg changed);
Thank you
Ngocman