Is it possible to make sub-micro seconds level timing control?

Hello,

I have a quick question.

In UHD, is it possible to give a nano second level timing control in
timed_tx samples
sample?
I think that is possible due to the restriction from OS,
but I saw some consistent difference in the transmission when I gave
timed
delay as

1.000000100, 1.000000200, and 1.000000210

In UHD, is it possible to give a nano second level timing control in
timed_tx samples
sample?

It is possible to specify times to the precision of the FPGA clock. See
http://www.ettus.com/uhd_docs/doxygen/html/classuhd_1_1time__spec__t.html

I think that is possible due to the restriction from OS,

Timed transmission is supported by the FPGA for all USRP models with the
exception of USRP1 classic:
http://www.ettus.com/uhd_docs/manual/html/usrp1.html#missing-and-emulated-features

-josh

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