Is it possible to change the sampling rate of D/A converter

GNU Radio
1

Dear all,

Is it possible to change the sampling rate of D/A converter to 64MHz? I
saw the sampling rate of D/A converter is defined in usrp_basic.cc,
which is fpga_master_clock_freq() * 2. Is it possible to make the master
clock frequency not multiply by 2? Can it be changed in python when the
flow gragh for the whole system is built.

Thank you so much in advance.

Regards,
Yan

2

On Wed, Jun 23, 2010 at 11:27 AM, Yan N. [email protected] wrote:

Is it possible to change the sampling rate of D/A converter to 64MHz? I saw
the sampling rate of D/A converter is defined in usrp_basic.cc, which is
fpga_master_clock_freq() * 2. Is it possible to make the master clock
frequency not multiply by 2?

Will setting the interpolation (sample rate) not suffice for your
application?

usrp_basic_tx::set_fpga_tx_sample_rate_divisor()

or

usrp_standard_tx::set_interp_rate()

Can it be changed in python when the flow gragh for the whole system is built.

certainly the interp parameter can be changed in python easily.

Also consider the rational_resampler block if integer interpolation
rates do not meet your sample rate requirements.

Jason