Is it possible to change ADC/DAC rates?

Say from 100MHz to 88MHz?

On Wed, 24 Jun 2009, Colby B. wrote:

Say from 100MHz to 88MHz?

Have you purchased a flux capacitor from Ebay?

:slight_smile:

This question is relating to the USRP2. I apologize for leaving that
detail
out.

Colby B. wrote:

Say from 100MHz to 88MHz?

You would need to change out the oscillator. There are pin compatible
ones with some other frequencies like 80 MHz, 122.88, and some others.
There is no 88 MHz one, but you could get a custom one from the
manufacturer if you needed. That’s an odd frequency, though. Why do
you need 88?

Matt

Ah OK. Just wondering for my own purposes. I’ve never really dealt with
ADC/DACs hands on before. They were always magical black boxes in my
undergrad DSP/Comm theory coursework. =) Should of taken a VLSI course
or
something.

I will be able to meet my needs with upsample/downsample + filtering.
Just
seeing if there was a short cut ;).

Thanks for your feed back Matt.

hi
i want to see the signals on the scope before and after modulation. but
the
transmit_path.py use hier_block2 and benchmark_tx use top_block. can any
one
kindly help on where should i go ahead and make changes?


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On Tue, Aug 11, 2009 at 08:59:23AM -0700, udadidd wrote:

hi
i want to see the signals on the scope before and after modulation. but the
transmit_path.py use hier_block2 and benchmark_tx use top_block. can any one
kindly help on where should i go ahead and make changes?

May I suggest logging the data to a file using gr.file_sink(…)
then examining it using octave, scipy, …

Eric

Thats cute.

I am serious though.

On 6/24/09, Daniel O’Connor [email protected] wrote:

“The nice thing about standards is that there
are so many of them to choose from.”
– Andrew Tanenbaum
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Sent from my mobile device

Sorry, Thats PORT B ALREADY in USE

udadidd wrote:

On Tue, Aug 11, 2009 at 08:59:23AM -0700, udadidd wrote:


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sure i can do that.
But my connections are like this…

self.connect(module A, module B, file_sink.1)
self.connect(module A,module B, module C)

self.connect (module C, module D, file_sink.2 )
self.connect (module C, module D, module E)

So now if i try to insert file in between my connections, it says, the
port
C already in use!!
So is there a way i can tap the data at these points?

Eric B. wrote:

May I suggest logging the data to a file using gr.file_sink(…)


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On Tue, Aug 11, 2009 at 02:18:15PM -0700, udadidd wrote:

sure i can do that.
But my connections are like this…

self.connect(module A, module B)
self.conenct(module B, module C)
self.connect(module B, file_sink.1)

self.connect(module C, module D)
self.connect(module C, file_sink2)

Eric

On Tue, Aug 11, 2009 at 02:19:02PM -0700, udadidd wrote:

Sorry, Thats PORT B ALREADY in USE

An output port may have any number of inputs connected to it.

Eric

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