Interfacing new USRP2 modules to the ZPU

Hi folks,

I’m trying to incorporate some custom DSP modules into the USRP2 FPGA
bitstream. I’m using a USRP2 rev 4, ISE 12.4, and the UHD project in
fpga/usrp2/top/u2_rev3 as a starting point. I’ve removed vita_tx_chain
due to space constraints, but the rest of the bitstream is intact.

My modules use a parallel interface for configuration. For testing, I’ve
been bit-banging them through a clunky Chipscope VIO; all works fine.
The next step is to transfer control to the ZPU: I plan to connect a
GPIO to Slave 9 of wb_1master, and write a module to interface between
this and my DSP stuff. I’d then add to the ZPU firmware to control the
GPIO, with the aim of eventually controlling my modules using the UHD
driver framework.

I can probably figure most of this out, but the ZPU code is in VHDL (I’d
prefer to stick with Verilog). Could you please tell me what I’d need to
modify in the ZPU’s HDL/memory map/firmware to add a GPIO? Also,
a bit of advice/info about the USRP2 peripheral interfacing ‘philosophy’
would be very helpful.

Finally, will the coming UHD changes affect the firmware and/or
bitstream of the USRP2 in any major way? Should I wait for the latest
firmware and port my modifications, or will the job be easy enough that
I can continue for now?

I’m a very new user, so any general development advice is appreciated.
Apologies for the vagueness of this post. Thanks for your help,

Vlad

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