Inquiry about automatic gain control

#1

I am trying to achieve a goal of controlling the AGC, please help.

Here is what I have so far, for the automatic gain control (AGC):

I have found in the module adc_interface (which is in
fpga\sdr_lib\adc_interface) a comment about level sensing for the AGC.

I am assuming the module rssi and module adc_interface is where the AGC
is
controlled?

If not where do I go about turning on or off the AGC. The rssi is used
to sense
the signal strength in the fpga and that is feedback to the ADC which
controls
the AGC, is that correct?

After I know how to turn on and off the AGC, how do I adjust the gain of
the
amplifier?

If I wanted to make a block diagram, or refer to a schematic that
involves the
AGC, where should I start?

Is the AGC located before the ADC, and the ADC is contained in the fpga,
right?

Thank you so much for your time and help,

Benjamin Dannan

#2

On Mon, Dec 1, 2008 at 10:53 PM, removed_email_address@domain.invalid wrote:

If not where do I go about turning on or off the AGC. The rssi is used to sense
the signal strength in the fpga and that is feedback to the ADC which controls
the AGC, is that correct?

I don’t believe there is any AGC actually going on at all. Please see
here:

http://gnuradio.org/trac/ticket/66

After I know how to turn on and off the AGC, how do I adjust the gain of the
amplifier?

You need to familiarize yourself with the gain settings of the
different daughterboards and how their gains are controlled.

The Python db code is probably a good place to start looking.

If I wanted to make a block diagram, or refer to a schematic that involves the
AGC, where should I start?

Is the AGC located before the ADC, and the ADC is contained in the fpga, right?

The ADC is an external chip. The data feeds into the FPGA where it is
then processed.

Thank you so much for your time and help,

Good luck.

Brian

#3

Brian,

Can AGC be implemented in code, on the verilog side using the FPGA?

Thanks

-Benjamin

uoting Brian P. removed_email_address@domain.invalid:

#4

Brian,

If you refer to the usrp\fpga\sdr_lib\adc_interface.v

this is a comment stating: \level sensing for AGC
on line 67 of the verilog code file.

I have read on the wiki that AGC can be implemented by moving resistors
around,
can you elaborate on this: which resistors, and on what board?

I am assuming that there is some sort of feedback loop for the FPGA to
an
amplifier which uses the RSSI, is there not one?

Thanks for your time and help.

-Benjamin Dannan

Quoting Brian P. removed_email_address@domain.invalid:

#5

removed_email_address@domain.invalid wrote:

I am assuming that there is some sort of feedback loop for the FPGA to an
amplifier which uses the RSSI, is there not one?

By moving some resistors around you can implement a completely analog
AGC function on the RFX900, 1200, 1800, and 2400. It will not work on
the RFX400.

In general, there are many ways you can implement AGC, depending on
where you implement the RSSI sensing and the control functions. Nothing
has been done to prevent you from doing any of these, but it is an
exercise left to the user, as they say.

Matt

#6

Matt,

So it is possible to be implemented in code on the verilog side? If so,
do you
have any suggestions on where to start?

Thanks for your help

Regards,
Benjamin Dannan
Quoting Matt E. removed_email_address@domain.invalid: