Input Clock For FPGA


#1

Hi Dear all Friends
I have some questions regardin schematic of GNU Radio
1- what is exact voltage of DVDD_CLK:1 and VREF_CLK:1 and othe such
lables I
could not find that?
2- since master clock is comming from OUT0 of AD9513 what is the input
frequency for CLK pin of AD9513? since I guess that OUT0 is devided by 6
based on S0-S10 pin status, however I can not get the exact input value
for
CLK (pin2) of AD9513!
can anybody help me as soon as possible?
thanks
regards


#2

Fahimeh Rezaei wrote:

Hi Dear all Friends
I have some questions regardin schematic of GNU Radio
1- what is exact voltage of DVDD_CLK:1 and VREF_CLK:1 and othe such
lables I could not find that?

DVDD_CLK is 3.3V. VREF_CLK is generated by the clock chip, and its
exact voltage doesn’t matter. It is somewhere around 2.2V.

2- since master clock is comming from OUT0 of AD9513 what is the input
frequency for CLK pin of AD9513? since I guess that OUT0 is devided by 6
based on S0-S10 pin status, however I can not get the exact input value
for CLK (pin2) of AD9513!
can anybody help me as soon as possible?

Both the input and output clocks are all 64 MHz.

Matt