Here is a diagram of the Rx side.
I plan to use a fifo to cross clock domains because it’s simpler than a
delay cell. Samples and commands will be stored in dual port fifos (one
per channel) A reader will poll them: if there are samples or commands,
push one single packet then poll next fifo. This should give a fair
share of the USB bandwidth to all channels/commands. I think I will be
able to reuse most of the code in the current rx_buffer that deals with
the FX2 DMA engine and the samples format, so the only task left is
building the packet itself.
Any comments, concerns ?