Inband FPGA rx/tx module communications

I’m a bit confused by the communication signals between the rx and tx
buffers. Maybe it’s the names that are throwing me. Can anyone help
explain the design?

Inband communication signals (from rx buffer):
input [15:0] rx_databus //data from inband_tx
input rx_WR //tx has data ready
input rx_WR_done //data packet from tx is
complete (go ahead and send it)

output reg rx_WR_enabled //send tx data every master_clock
while active

What is “WR”? I am reading this as “Write/Read”. But I only see
communication. Hmmm, maybe “Write Register”? That fits I guess.

Protocol like this?:

Tx: set rx_WR (signal we have data)
Rx: set rx_WR_enabled (start sending)
Tx: send data on every master_clock
Tx: set rx_WR_done (signal packet done)
Rx: clear rx_WR_enabled (waiting for next rx_WR)
Tx: clear rx_WR_done
Tx: clear rx_WR (if no more data?)

Must Tx clear rx_WR after each packet, even if there is another packet
to go?

I assume it would be illegal for rx_WR_done and rx_WR_enabled to be set
together for more than one tick? rx_WR_done should only be set for one

What is the proper behavior of Tx if Rx does not clear the rx_WR_enabled
after rx_WR_done?

What if Rx clears rx_WR_enabled while rx_WR is set? (before complete
is sent)


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