Icarus simulation help

Hi

I want to write a testbench for phase_acc.v to help me to get started
in simulating the whole decimation scheme. So this is the phase_acc.v
file:

module phase_acc
(clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
`include “setting_reg.v”
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;

input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;

output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;

setting_reg #(FREQADDR)
sr_rxfreq0(.clock(clk),.reset(1’b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));

always @(posedge clk)
if(reset)
phase <= #1 32’b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;

endmodule // phase_acc

I’ve looked at quite a few icarus and gtkwave examples. I would just
like to know how I do the whole

setting_reg #(FREQADDR)
sr_rxfreq0(.clock(clk),.reset(1’b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));

part. Setting_reg’s verilog code is in setting_reg.v. How do I write
a testbench for the phase accumulator so that the line where
sr_rxfreq0 is instantiated works? Obviously I’ll only have this:
module phase_acc
(clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
in my testbench file. When I try to compile it, I get the following
error:

phase_acc.v:41: error: Unknown module type: setting_reg
Elaboration failed
*** These modules were missing:
setting_reg referenced 1 times.


I’ve tried adding 'include “setting_reg.v” in phase_acc.v, but then I
get the following error:

setting_reg.v:3: syntax error
setting_reg.v:3: error: invalid module item. Did you forget an initial
or always?
phase_acc.v:29: syntax error

Thank you very much.

Sebastiaan

Attached is a simple testbench.

Here is what I have in my directory and how I run:

$ ls *.v
phase_acc.v phase_acc_tb.v setting_reg.v

$ iverilog *.v ; ./a.out > output ; cat output
123456
2952913472
1610736192
268558912
3221348928
1879171648
536994368
3489784384
2147607104
805429824
3758219840
2416042560
1073865280
4026655296
2684478016
1342300736
123456
End of simulation

Brian

Brian

Thanks again for the testbed file. I see what phase_acc does now.
When we do a downconversion, the initial phase that gets written to
the FR_RX_PHASE_0 register is 0, right? I just want to make sure of
that and that the phase value repeats after about 16 clock cycles. I
would just like to know if you know of a good testbed tutorial around.
What I would like to do now is generate a sine wave at 20MHz, sampled
at 64MHz and save this to a text file. I would also like to save the
phase values generated by phase_acc to a text file. I then want to
write a testbench for cordic.v with the incoming sine wave and phase
values and save the output from the cordic to a text or datafile. If
you know how to access and read/write files in Iverilog, could you
please just show me a line of code or two to do it?

Thank you very much.

Sebastiaan H.

On Thu, Aug 28, 2008 at 5:07 PM, Sebastiaan H. [email protected]
wrote:

write a testbench for cordic.v with the incoming sine wave and phase
values and save the output from the cordic to a text or datafile. If
you know how to access and read/write files in Iverilog, could you
please just show me a line of code or two to do it?

Sure, but phase is pretty arbitrary anyway, right?

No need for all the files. Just instantiate all the components you
want to test in the same testbench. Then you have one test which
tests everything.

As for writing testbenches, Google really is your friend - or the GNU
Radio repository - or any sort of other examples.

I don’t mind answering your questions, but you should give yourself
some credit and give it a shot.

Thank you very much.

You’re welcome. Good luck.

Brian

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