Hi
I want to write a testbench for phase_acc.v to help me to get started
in simulating the whole decimation scheme. So this is the phase_acc.v
file:
module phase_acc
(clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
`include “setting_reg.v”
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR)
sr_rxfreq0(.clock(clk),.reset(1’b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32’b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
I’ve looked at quite a few icarus and gtkwave examples. I would just
like to know how I do the whole
setting_reg #(FREQADDR)
sr_rxfreq0(.clock(clk),.reset(1’b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
part. Setting_reg’s verilog code is in setting_reg.v. How do I write
a testbench for the phase accumulator so that the line where
sr_rxfreq0 is instantiated works? Obviously I’ll only have this:
module phase_acc
(clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
in my testbench file. When I try to compile it, I get the following
error:
phase_acc.v:41: error: Unknown module type: setting_reg
Elaboration failed
*** These modules were missing:
setting_reg referenced 1 times.
I’ve tried adding 'include “setting_reg.v” in phase_acc.v, but then I
get the following error:
setting_reg.v:3: syntax error
setting_reg.v:3: error: invalid module item. Did you forget an initial
or always?
phase_acc.v:29: syntax error
Thank you very much.
Sebastiaan