How you can help on the USRP2 effort

A number of people have asked how they can help out on the USRP2
development effort. For now, we have the following:

First, the USRP2 FPGA will have a microprocessor core in it. The one we
have been using has a couple of issues, most notably that it seems to
only run at around 33 MHz. The main USRP2 clock is 100 MHz, so it would
be nice if we had a processor which could handle at least 50 MHz. There
are 2 options here – investigate why the current processor core is
having trouble running faster, or investigate an alternative processor
core which I have identified. The first one involves running the Xilinx
tools and analyzing the timing paths. The second involves building
cross compilers and running already-existing tests in icarus verilog to
confirm that the new core really works before we use it.

Secondly, I have been using the Xilinx GUI-based tools for running
synthesis, place and route, etc. However, I don’t get consistent
results using them, and even multiple routes of the same design give
widely varying results. It would be nice to have text-based compile
scripts which I could count on doing the same thing every time. Maybe
even a makefile. This would be an ideal task for someone familiar with
the xilinx tools under linux.

Third would be to investigate some timing issues I am seeing, which I
believe could be fixed by correctly specifying some Xilinx timing
constraints, and/or correctly choosing synthesis and place & route
options. Again, someone familiar with the Xilinx tools would be best
equipped to take this on.

If you are interested in helping with any of these tasks, please send me
an email off-list for more details.