I am newbie to USRP (N210) i want to modify its FPGA core for timing
synchronization of MIMO as project.
I downloaded “EttusResearch-UHD-Mirror-release_003_003_001-197-ge30cf4e”
this and using xilinx 13.1 in window XP. . but my simulation is not
properly i just made project and add required file to project in
(top level to down each an every file which are used in any module). But
simulation is not working properly test bench is also given by “Ettus”.
Google it a lot but no source of information
Please you guys help me from where did I start
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