How to update FPGA in E100

Hi, all,

We have made a FPGA FFT module.
We downloaded the UHD source code from
https://github.com/EttusResearch/UHD-Mirror/archives/master
We modified the usrp_std.v under
fpga/usrp1/toplevel/usrp_std/
to link our FFT module between rx_buffer and USB.
We have successfully compiled the usrp_std.qpf in Quartus II 9.1.
How can we make it effective in our USRP E100?

We found the way to update FPGA firmware in usrpe1xx-FAQ
http://ettus-apps.sourcerepo.com/redmine/ettus/projects/usrpe1xx/wiki/FAQ?version=30
But what we want to update is the FPGA code.

Thanks a lot!

Yooxi

On 08/24/2011 09:30 PM, xi yang wrote:

Hi, all,

We have made a FPGA FFT module.
We downloaded the UHD source code from
https://github.com/EttusResearch/UHD-Mirror/archives/master
We modified the usrp_std.v under
fpga/usrp1/toplevel/usrp_std/
to link our FFT module between rx_buffer and USB.
We have successfully compiled the usrp_std.qpf in Quartus II 9.1.
How can we make it effective in our USRP E100?

You build images for the USRP1. That is a different product than E100.

Pre-built images are here:
http://code.ettus.com/redmine/ettus/projects/uhd/wiki#Binary-downloads

Installation notes:
http://ettus.dyndns.org/uhd_docs/manual/html/images.html#archive-install

The verilog source can be found here:
http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/show/fpga/usrp2/top/E1x0

-josh

Yooxi,

The USRP1 used an Altera FPGA. The USRP E100 uses a Xilinx Spartan-3A
FPGA.
The FPGA code you want to be modifying is in the fpga/usrp2/top/E1x0
directory.

–n

Hi, Nick,

Thanks a lot!
Do you know which file is same as usrp_std.v that is responsible for
binding
all modules together?

Yooxi

2011/8/25 Nick F. [email protected]

On 08/25/2011 03:26 PM, xi yang wrote:

Hi, Nick,

Thanks a lot!
Do you know which file is same as usrp_std.v that is responsible for binding
all modules together?

This one:

fpga/usrp2/top/E1x0/u1e_core.v

I think.

Philip

Hi, Philip,

Thanks!
If I got a USRP1, what files do I need to copy to /usr/share/uhd/images
?
And that’s it? No additional operations?

Yooxi

2011/8/25 Philip B. [email protected]

On 08/25/2011 03:41 PM, xi yang wrote:

Hi, Philip,

Thanks!
If I got a USRP1, what files do I need to copy to /usr/share/uhd/images ?
And that’s it? No additional operations?

Are you using a USRP1 or a USRP-E100?

Philip

Thanks, Josh!
Then we will find a Xilinx ISE and see what’s the next step.

Yooxi

Josh B.-3 wrote:

fpga/usrp1/toplevel/usrp_std/
http://ettus.dyndns.org/uhd_docs/manual/html/images.html#archive-install


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Hi,

We are using USRP-E100, but that requires us to find a Xilinx ISE first.
We will go on that but since we can get a USRP1,
we want to know how to update FPGA on USRP1 too.

We have already successfully compiled it in Quartus, and we want to have
a test first.
The file and the only file we have modified is the usrp_std.v and we
complied the project usrp_std.qpf.
No file under fpga/usrp1/toplevel/usrp_std/ is similar to that
under /usr/share/uhd/images.
But instruction says
The UHD will always search /share/uhd/images for image
files
http://files.ettus.com/uhd_docs/manual/html/images.html#archive-install

What files do we need to copy and to which place should we copy them
from
fpga/usrp1/toplevel/usrp_std/?
Previously, we will compile a project and load it to the device through
JTAG.
For USRP1, what should we do?

Thanks,
Yooxi

On 08/25/2011 03:41 PM, xi yang wrote:

Hi, Philip,

Thanks!
If I got a USRP1, what files do I need to copy to /usr/share/uhd/images ?
And that’s it? No additional operations?

Are you using a USRP1 or a USRP-E100?

Philip

Yooxi


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