 # How to learn of decimation rate in general_work()?

I am using stream tags to get the timestamp of its corresponding sample
in
general_work(). Now, if I want to calculate the time of an arbitrary
sample in the incoming sample stream I need to know the decimation rate.
This tells me how much clock time is added per-sample. So I can
calculate
the offset between the timestamped sample and the sample I care about,
and
then multiple that offset by the time per sample.

Is there a good way to learn of the decimation rate in general_work() to
do
this?

On Thu, Jan 19, 2012 at 3:09 PM, George N. [email protected]
wrote:

I am using stream tags to get the timestamp of its corresponding sample in
general_work(). Now, if I want to calculate the time of an arbitrary
sample in the incoming sample stream I need to know the decimation rate.
This tells me how much clock time is added per-sample. So I can calculate
the offset between the timestamped sample and the sample I care about, and
then multiple that offset by the time per sample.

Is there a good way to learn of the decimation rate in general_work() to
do this?

Hey George,

You can use the relative_rate data member of the blocks. Setting the
decimation actually sets the relative_rate to 1.0/decimation. You can
get
this value with the accessor function “relative_rate()”.

Hey George,

You can use the relative_rate data member of the blocks. Setting the
decimation actually sets the relative_rate to 1.0/decimation. You can get
this value with the accessor function “relative_rate()”.

Hey Tom,

Using this I can get the decimation rate, but is there a way to get the
rate of samples from the ADC? That way I can compute the real clock
time
in-between samples. For the USRP2, despite the ADC running running at
400Msps, it’s rate through the FPGA is actually 100Msps, right?

Just to confirm, the USRP2/N2x0 ADC samples at 100MHz. (The DAC output
however runs at 400MHz, its fed samples at 100MHz and it has built in 4x
interpolation which may be the source of confusion).

On Wed, Feb 8, 2012 at 7:34 PM, Ian B. [email protected]
wrote:

400Msps, it’s rate through the FPGA is actually 100Msps, right?

Actually, I think the ADC is running at 100 Msps, which I think you can
get with the “get_clock_rate(mboard)” method. The rate that they come
across is then determined by the decimation rate. You can query sample rate
from the USRP via the UHD with the “get_sampl_rate()” method.

Great, thanks a bunch for the info Tom & Ian! I’m using UHD, so I will
use get_sampl_rate()

On Tue, Feb 7, 2012 at 5:37 PM, George N. [email protected] wrote:

Using this I can get the decimation rate, but is there a way to get the
rate of samples from the ADC? That way I can compute the real clock time
in-between samples. For the USRP2, despite the ADC running running at
400Msps, it’s rate through the FPGA is actually 100Msps, right?

Actually, I think the ADC is running at 100 Msps, which I think you can
get
with the “get_clock_rate(mboard)” method. The rate that they come across
is
then determined by the decimation rate. You can query sample rate from
the
USRP via the UHD with the “get_sampl_rate()” method.

Tom

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