Does anyone know just how much resources will be freed up by doing the
following (this is one of the FPGA/Verilog questions on the wiki)?
-
- I went through the mailing list and figured out that the current
Verilog/VHDL code implementation occupies 95% of FPGA’s resources.
However,
there were some mails that pointed that reducing some receiver
functionalities could free some FPGA resources. How? *
- I went through the mailing list and figured out that the current
The header file config.vh (trunk?) controls the build configuration and
is
now functional. Modify it to use the file:
…/include/common_config_1rxhb_1tx.vh. This is how:
// Uncomment this for 1 RX channel (w/ halfband) & 1 transmit channel
`include “…/include/common_config_1rxhb_1tx.vh”
This will free up a lot of space on the FPGA for experimentation!
Curious if anyone had done this.
Thanks,
–
Newell
http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits