How is the FPGA taking effect in USRP?!

Hello, everyone

I dug up the wfm_rcv_gui.py example file in order to penetrate the
principle of GNURadio. But I have 2 questions about it:

1, there is a digital downconverter at the receiver, the function of
down converting the signal is performed by the FPGA or the software on
PC?

2, if it is done by FPGA, how is the code transmitted to the FPGA? I
mean, the code should be written using VHDL or Verilog, but now the code
is compiled using Python! How is this transformation done?

Thank u!!!

#!/usr/bin/env python

from gnuradio import gr, eng_notation
from gnuradio import audio
from gnuradio import usrp
from gnuradio import blks
from gnuradio.eng_option import eng_option
from optparse import OptionParser
import sys
import math

from gnuradio.wxgui import stdgui, fftsink
import wx

class wfm_rx_graph (stdgui.gui_flow_graph):
def init(self,frame,panel,vbox,argv):
stdgui.gui_flow_graph.init (self,frame,panel,vbox,argv)

    IF_freq = parseargs(argv[1:])
    adc_rate = 64e6

    decim = 250
    quad_rate = adc_rate / decim               # 256 kHz
    audio_decimation = 8
    audio_rate = quad_rate / audio_decimation  # 32 kHz

    # usrp is data source
    src = usrp.source_c (0, decim)
    src.set_rx_freq (0, IF_freq)[email protected]
    src.set_pga(0,20)

    guts = blks.wfm_rcv (self, quad_rate, audio_decimation)

    # sound card as final sink
    audio_sink = audio.sink (int (audio_rate))

    # now wire it all together
    self.connect (src, guts)
    self.connect (guts, (audio_sink, 0))

    if 1:
        pre_demod, fft_win1 = \
                   fftsink.make_fft_sink_c (self, panel, 

“Pre-Demodulation”,
512, quad_rate)
self.connect (src, pre_demod)
vbox.Add (fft_win1, 1, wx.EXPAND)

    if 1:
        post_deemph, fft_win3 = \
                     fftsink.make_fft_sink_f (self, panel, "With 

Deemph",
512, quad_rate, -60,
20)
self.connect (guts.deemph, post_deemph)
vbox.Add (fft_win3, 1, wx.EXPAND)

    if 1:
        post_filt, fft_win4 = \
                   fftsink.make_fft_sink_f (self, panel, "Post 

Filter",
512, audio_rate, -60,
20)
self.connect (guts.audio_filter, post_filt)
vbox.Add (fft_win4, 1, wx.EXPAND)

def parseargs (args):
nargs = len (args)
if nargs == 1:
freq1 = float (args[0]) * 1e6
else:
sys.stderr.write (‘usage: wfm_rcv freq1\n’)
sys.exit (1)

return freq1 - 128e6

if name == ‘main’:
app = stdgui.stdapp (wfm_rx_graph, “WFM RX”)
app.MainLoop ()

  ____________________________________________________________________________________

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On Mon, Mar 17, 2008 at 9:07 PM, Eric B. [email protected] wrote:

There are two downconverions, one in the RF daughterboard, and one in

The firmware for the FX2 (usb interface chip) and the FPGA
configuration are loaded behind the scenes by the usrp library which
is invoked by usrp.sink*/source

Eric

This might help you better understand the connections between various
components. http://www.nd.edu/~jnl/sdr/docs/

Karthik

On Mon, Mar 17, 2008 at 08:59:54PM -0700, Bill S. wrote:

Hello, everyone

I dug up the wfm_rcv_gui.py example file in order to penetrate the
principle of GNURadio. But I have 2 questions about it:

1, there is a digital downconverter at the receiver, the function of
down converting the signal is performed by the FPGA or the software
on PC?

There are two downconverions, one in the RF daughterboard, and one in
the DDC in the FPGA.

See http://gnuradio.org/trac/wiki/UsrpRfxDiagrams

2, if it is done by FPGA, how is the code transmitted to the FPGA? I
mean, the code should be written using VHDL or Verilog, but now the
code is compiled using Python! How is this transformation done?

If you take a look through the downloaded source code, you’ll find the
verilog for the FPGA in usrp/fpga.

The firmware for the FX2 (usb interface chip) and the FPGA
configuration are loaded behind the scenes by the usrp library which
is invoked by usrp.sink*/source

Eric

On Tue, Mar 18, 2008 at 02:10:30AM -0700, Karthik Vijayraghavan wrote:

On Mon, Mar 17, 2008 at 9:07 PM, Eric B. [email protected] wrote:

This might help you better understand the connections between various
components. http://www.nd.edu/~jnl/sdr/docs/

Please note that that document was written two years ago, we don’t
control it, and we can’t update it. YMMV.

Eric

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