It seems that there is a very significant roll-off at lower
frequencies on the receive side which pretty much makes it unusable
for our baseband signals.
The aformentioned forum post suggests that it is not caused by the
LFRX board and so is likely to be something in the fpga…
Just to reiterate the questions from this forum post.
What on the FPGA is causing this frequency response? (and what can
we do about it?)
Why does this happen only in the RX path?
And the original poster also wanted to know:
3) According to http://gnuradio.org/redmine/wiki/1/USRP2GenFAQ reference:
“How can I use both A/D converters on the USRP2?”
feeding the signal to RX_B does not give ANY output on the ADC
If anyone can offer any help at all with this it’d be much appreciated.
Thanks,
Drew
–
Andrew Read +64 (03) 357 0787
Test Analyst
Design Verification and Validation Team
Tait Electronics Ltd
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feeding the signal to RX_B does not give ANY output on the ADC
If anyone can offer any help at all with this it’d be much appreciated.
Thanks,
Drew
I can’t speak for your flowgraph, but the referenced flow-graph in your
post is mis-constructed
in a couple of difference ways.
The USRP2 input decimation is set to ‘101’ – odd decimations in USRP2
are not recommended.
Plus, neither the SCOPE sink nor the FFT sink have been told the
correct sample rate, so lord
knows what they’re actually showing in terms of frequency response.
In USRP2, even decimation, preferrably a multiple of 4.
I’ve noticed no low-frequency rolloff in my applications with either the
USRP1 or USRP2.
–
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
You’re probably seeing the high-pass behavior of the RX DC offset
removal. There’s a logical block inside the FPGA which integrates the
ADC DC offset and subtracts it from the incoming signal.
This function isn’t needed on the TX side.
Would it have such a high corner-frequency, though? Seems like the DC
estimate integrator function
could easily be arranged to have a corner frequency much lower than
1KHz. But maybe I’m
wrong.
–
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
Yes! that seems to be doing it.
After using u.set_dc_offset_cl_enable(0x0, 0xf) to disable the dc
correction the Low Freq roll-off seems to be gone and my IQ looks a
lot better.
That’s really excelent, I presume I’ll still need to compensate for
the dc in my flow graph now though…
Many thanks!
Drew
On Fri, Nov 5, 2010 at 1:08 PM, Marcus D. Leech [email protected]
wrote:
–
Andrew Read +64 (03) 357 0787
Test Analyst
Design Verification and Validation Team
Tait Electronics Ltd
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the subject of legal or other privilege, none of which is waived or
lost by reason of this transmission.
If the receiver is not the intended addressee, please accept our
apologies, notify us by return, delete all copies and perform no
other act on the email.
Unfortunately, we cannot warrant that the email has not been
altered or corrupted during transmission.
You’re probably seeing the high-pass behavior of the RX DC offset
removal. There’s a logical block inside the FPGA which integrates the
ADC DC offset and subtracts it from the incoming signal.
This function isn’t needed on the TX side.
Eric
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