Hi
I’ve been bashing my head against this problem for a few weeks now, but
I can’t seem to figure it out. I’ve been making a few modifications to
the verilog code, in particular the tx_buffer.v module. What I want to
do is send a signal from the pc and trap it in the fpga. I’ve tried
doing this by replacing the FIFO module with an ALTSYNCRAM module
(generated by quartus). The idea is to capture the incoming signal in
the RAM, and only transmit it when an external trigger is received. (for
the external signal, I am using a changing register for now). I am using
a slightly modified version of the test_usrp_standard_tx program to test
my FPGA build. So far though, none of the signals I’ve tried to send
have been transmitted (I have a scope on the daughterboard output).
Below is the modified module:
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input ptr_reset, //reset the read pointer to transmit same signal
again
input [15:0] usbdata,
input wire WR,
output wire have_space,
output wire done, //indicates when the whole waveform has been sent
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
input start, //start sending the waveform
output [15:0] debugbus
);
reg [8:0] write_count;
wire [15:0] ramdata;
wire rdreq;
reg [11:0] wrptr; //write address
reg [11:0] rdptr; //read address
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & start);
assign done = (rdptr == wrptr);
always @(posedge txclk)
if(reset | ptr_reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128’h0;
load_next <= #1 4’d0;
rdptr <= #1 12’d0;
end // (reset |ptr_reset)
else
if((load_next != channels) & start)
begin
rdptr <= #1 rdptr + 1;
load_next <= #1 load_next + 4’d1;
case(load_next)
4’d0 : tx_i_0 <= #1 ramdata;
4’d1 : tx_q_0 <= #1 ramdata;
4’d2 : tx_i_1 <= #1 ramdata;
4’d3 : tx_q_1 <= #1 ramdata;
4’d4 : tx_i_2 <= #1 ramdata;
4’d5 : tx_q_2 <= #1 ramdata;
4’d6 : tx_i_3 <= #1 ramdata;
4’d7 : tx_q_3 <= #1 ramdata;
endcase // case(load_next)
end // if ((load_next != channels) & start)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4’d0;
end
// USB Side of FIFO
assign have_space = 1’b1; //quick fix for now. (wrptr <= 4000) not
functioning
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(reset)
wrptr <= #1 12’d0;
else if(WR & ~write_count[8])
begin
wrptr <= #1 wrptr + 1; //move to next address to write
write_count <= #1 write_count + 9’d1;
end
else
write_count <= #1 WR ? write_count : 9’b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1’b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1’b1;
else if(clear_status)
tx_underrun <= 1’b0;
// RAM
signal_ram signal_ram
( .data ( usbdata ),
.wren ( WR & ~write_count[8] ),
.wrclock ( usbclk ),
.wraddress ( wrptr ),
.q ( ramdata ),
.rden ( rdreq ),
.rdclock ( txclk ),
.rdaddress ( rdptr ),
.wr_aclr ( reset ), // asynch, so we can use either
.rd_aclr ( reset )
);
// Debugging Aids
assign debugbus[11:0] = wrptr;
assign debugbus[12] = start;
assign debugbus[13] = rdreq;
assign debugbus[14] = done;
assign debugbus[15] = ptr_reset;
endmodule // tx_buffer
It’s probably something simple I’ve missed, I’m pretty new to verilog.
Any help would be greatly appreciated.
Regards
Lance