Help with DSP Cores for USRP2

I could use some help creating some DSP cores for the USRP2 since I’m
very busy with other parts of the design. Some basic parameters:

Clock Rate – 100 MHz
Sample format – 16 or 18 bit 2’s complement
When sample streams are at a rate lower than 100 MS/s, valid samples are
accompanied by a strobe signal
Use distributed RAM or SRL16s, but not block RAM
You can use hard multipliers or distributed arithmetic
Filter taps should be writable

Some cores which would be useful:

1 Halfband decimator
Samples should come in at a settable rate of up to one half the
clock rate and exit at half that rate (i.e. up to one fourth the clock
rate). You’ll probably need 2 hard multipliers. That gives you 8
multiplies per sample, giving you a 31-tap halfband filter.

2 Interpolator equivalent to the above.

3 For bonus points, make either of the above controllable such that at
lower sample rates they use the extra cycles to implement a 63-tap
halfband filter.

4 A decimate-by-5 filter which takes in samples at up to the full
clock rate and outputs them at 1/5 of that rate. It should not be a CIC
decimate-by-5 filter, but could be a CIC decimate by 2 followed by a
decimate-by-2.5 polyphase filter.

5 The interpolator equivalent of the above.

6 Testbenches for any of the above, even if you aren’t designing the
filter core itself.

I’d prefer not to use Xilinx cores, but you can use those to see what
sort of performance should be attainable.


On Jan 17, 2008 2:42 PM, Matt E. [email protected] wrote:

6 Testbenches for any of the above, even if you aren’t designing the
filter core itself.

I have put my attempt at a decent testbench here:

There are some parameterizations that can still happen (width of the
data in/out, normalization value on output, etc), but this should work
pretty well with checking if decimation or interpolation filters match
their ideal implementation (also included and not synthesizable).

Any feedback/recommended improvements are welcome.