# Help with Cordic.v

Hi All,

I needed some help with Verilog Cordic code.(cordic.v and
cordic_stage.v) I do understand the Cordic Logic, but was having some
trouble with the pipelined code implementation of cordic.v . My

## In cordic.v:

16 bit vector xi, yi and zi are passed as input. Then cordic
constants are pre-defined.

Q – Not sure what “wire [bitwidth+1:0] xi_ext =
{{2{xi[bitwidth-1]}},xi};” statement is doing. Is it just normal
concatenation and assignment?

Now, @posedge clock, if reset is set, then x0, y0, z0 is initialized
to ‘0’. Next, when enable is set, z0 is assigned all bits except the
first two. And the first 2 bits are used for the case statement.

Q – My understanding is that in this case statements, the first 2
quadrant (angle) for xi_ext and yi_ext by 90 or 180 or 270 or 360
degree… But I am not sure. Any comments ?

Then many instances of cordic_stage are defined and they are passed
input values x0, y0, z0 and constants c00 etc.

Q – I am not sure what “#(bitwidth+2,zwidth-1,0)” in this instance
definition does. My understanding is that # value is used to define
some delay.

## In cordic_stage.v

if reset is set then xo, y0 and zo are set to 0. And when enable is
set, value of z is checked. My understanding of cordic logic is that,
if say that current angle is 45, and desired is 20, then subtract from
the current angle, and make corresponding adjustments on x axis and y
axis variables.

Q – This statement checks if “z_is_pos” and does next operation
respectively. I am not sure what “xi -
{{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]}” is actually doing.
My understanding of cordic is that based on angle adjustments,
operations of multiples of 2 are carried out on x-axis and y-axis
variable. And {} statement are used for concatenation in verilog.

## Again, in cordic.v

xo, yo and zo are in continuous assignment mode and are updated
everytime a x12, y12 or z12 value changes respectively.

Q – Not exactly sure how the exact desired angle is obtained in
‘current angle’ so that it converged to the desired angle. I don’t see
that step happening in cordic.v

I am extremely sorry if I might have annoyed you by asking so many
questions. But, any help with the above questions will immensely help
me.

Thank you.

Ronald.

Ronald-

Q – Not sure what "wire [bitwidth+1:0] xi_ext =
degree… But I am not sure. Any comments ?

Then many instances of cordic_stage are defined and they are passed
input values x0, y0, z0 and constants c00 etc.

Q – I am not sure what “#(bitwidth+2,zwidth-1,0)” in this instance
definition does. My understanding is that # value is used to define
some delay.

It would seem that each cordic_stage instance has a rise delay of
bitwidth+2, fall
delay of zwidth-1, and turn-off delay one tick longer than the previous
stage. I
might guess this was helpful somehow during simulation debug… but it
doesn’t affect
synthesis / actual circuit behavior.

-Jeff

Ronald-

Thank you Jeff for your help !

Sure, but please keep in mind my answer was not correct. As Matt
pointed out,
cordic.v code is using #() to redefine parameters passed to cordic_stage
module
instances. These are constants, not signals.

My own opinion is that this use of # is confusing and there are other
ways, such as
defparam, that avoid confusion with the # token when it’s used for
simulator delays.

-Jeff